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The scaling of MOSFETs as dictated by the ITRS has continued unabated for many years and enabled the worldwide semiconductor market to grow at a phenomenal rate. However, the ITRS scaling is reaching hard limitations. One of the most significant problems is the maintenance of electrostatic integrity, which demands the use of extremely thin gate oxides to provide the required high gate capacitance, as well as the use of high channel doping to control short channel effects. These requirements lead to low device performance and tunneling current becomes quite prominent. This book introduces a promising solution to these problems, that is Double Gate MOSFET with high-k gate stack. This book provides an elaborate performance analysis of DG MOSFET with high-k material on both top and bottom gate stack in terms of drain current & subthreshold characteristics using 2D quantum simulator nanoMOS 4.0.
Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called “scaling”, has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore’s Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi?cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi?cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif?culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore’s law and each dif?culty has found a solution.
To push MOSFETs to their scaling limits and to explore devices that may complement or even replace them at molecular scale, a clear understanding of device physics at nanometer scale is necessary. Nanoscale Transistors provides a description on the recent development of theory, modeling, and simulation of nanotransistors for electrical engineers, physicists, and chemists working on nanoscale devices. Simple physical pictures and semi-analytical models, which were validated by detailed numerical simulations, are provided for both evolutionary and revolutionary nanotransistors. After basic concepts are reviewed, the text summarizes the essentials of traditional semiconductor devices, digital circuits, and systems to supply a baseline against which new devices can be assessed. A nontraditional view of the MOSFET using concepts that are valid at nanoscale is developed and then applied to nanotube FET as an example of how to extend the concepts to revolutionary nanotransistors. This practical guide then explore the limits of devices by discussing conduction in single molecules
This book consists of four chapters to address at different modeling levels for different nanoscale MOS structures (Single- and Multi-Gate MOSFETs). The collection of these chapters in the book are attempted to provide a comprehensive coverage on the different levels of electrostatics and transport modeling for these devices, and relationships between them. In particular, the issue of quantum transport approaches, analytical predictive 2D/3D modeling and design-oriented compact modeling. It should be of interests to researchers working on modeling at any level, to provide them with a clear explanation of theapproaches used and the links with modeling techniques for either higher or lower levels.
Written from an engineering standpoint, this book provides the theoretical background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOS nanoscale transistors. A wealth of applications, illustrations and examples connect the methods described to all the latest issues in nanoscale MOSFET design. Key areas covered include: • Transport in arbitrary crystal orientations and strain conditions, and new channel and gate stack materials • All the relevant transport regimes, ranging from low field mobility to quasi-ballistic transport, described using a single modeling framework • Predictive capabilities of device models, discussed with systematic comparisons to experimental results
Fundamentals of Nanoscaled Field Effect Transistors gives comprehensive coverage of the fundamental physical principles and theory behind nanoscale transistors. The specific issues that arise for nanoscale MOSFETs, such as quantum mechanical tunneling and inversion layer quantization, are fully explored. The solutions to these issues, such as high-κ technology, strained-Si technology, alternate devices structures and graphene technology are also given. Some case studies regarding the above issues and solution are also given in the book.
This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices. Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future – in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices. This book addresses the field of materials development, which has been the subject of a major research drive aimed at finding new ways to enhance the performance of semiconductor technologies. It covers three areas that will each have a dramatic impact on the development of future CMOS devices: global and local strained and alternative materials for high speed channels on bulk substrate and insulator; very low access resistance; and various high dielectric constant gate stacks for power scaling. The book also provides information on the most appropriate modeling and simulation methods for electrical properties of advanced MOSFETs, including ballistic transport, gate leakage, atomistic simulation, and compact models for single and multi-gate devices, nanowire and carbon-based FETs. Finally, the book presents an in-depth investigation of the main nanocharacterization techniques that can be used for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise, and Raman spectroscopy.
The limited benefits of strain engineering in extremely scaled silicon devices and a lack of demonstrated gain in performance at the product level in nanowires, nanotubes, graphene, and other exotic channel materials give good reason to continue semiconductor device scaling using high-transport III-V (such as InGaAs and InAsSb) channel materials beyond the year 2020. Novel process techniques, such as ALD, layer transfer, high- k dielectrics, and metal gates are now being used to explore these MOSFETs. III-V materials are also being investigated for possible use in quantum-mechanical devices (such as tunnel transistors), in spin-FET devices, and in qubits and memory cells. However, there are several challenges (such as, low ION /IOFF ratio) associated with III-V MOSFETs that prohibit their use in high-performance and low-power logic applications. To address some of these challenges, in this work, we investigate the performance of tri-gate III-V FETs (with 18nm and 9nm channel lengths) as compared to the single-gate counterparts, and show how quantum size-quantization and random dopant fluctuations (RDF) affect the tri-gate FET characteristics and how to curb these issues. For this purpose, a 3-D fully atomistic quantum-corrected Monte Carlo device simulator has been integrated and used in this work. The size-quantization effects have been accounted for via a parameter-free effective potential scheme and benchmarked against the NEGF approach in the ballistic limit. To study the RDF effects and treat full Coulomb (electron-ion and electron-electron) interactions in the real-space and beyond the Poisson picture, the simulator implements a corrected Coulomb electron dynamics (QC-ED) approach. The essential bandstructure and scattering parameters (bandgap, effective masses, and the density-of-states) have been computed using a 20-band nearest-neighbour sp3d 5s * tight-binding scheme. Among various III-V materials studied in this work (such as GaAs, GaSb, InAs, InSb, and InAsSb), InAs0.7 Sb0.3 , when used with appropriately engineered gate metal workfunction, was found to deliver the largest ION /IOFF ratio. As for the gate oxide, per the recipe of several experimental groups, to overcome the direct tunnel leakage current that accrues with using oxide thicknesses less than 2nm, SiO2 has been replaced with HfO2 . From the simulation results, ION with HfO2 was found to be approximately two times higher than that with SiO2 . For 18-nm channel length, the trigate architecture, as compared to the single-gate counterpart, offered better sub-threshold swing, higher (~2×) ON current, and reduced off-current at VDS = 0.5V. Of the various scattering mechanisms considered in the simulations, surface roughness was found to be most critical, which degraded the drive current by almost 34% and 22% in the single-gate and trigate devices, respectively. However, the effect of surface roughness diminishes drastically as the channel length is scaled down to 9 nm. On the flip side, small effective masses as observed in these material systems, although preferred for high mobility and injection velocity, results in a significant reduction in inversion layer charge. Additionally, small effective mass, especially in reduced dimensionality (nanowire) structures, leads to strong quantum mechanical effects and further degradation in the drive current. With regard to the intrinsic parameter fluctuation, it was found that, although both the planer and the tri-gate transistors experience some fluctuation in threshold voltage due to randomness in the channel region, this deviation is smaller in the trigate architecture. Finally, the random dopant fluctuation (RDF) effect was found to be weaker in a 9-nm channel device than the 18-nm counterpart.
According to Moore’s Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devices, and fabrication processes for high-k gate dielectric materials, Nano-CMOS Gate Dielectric Engineering systematically describes how the fundamental electronic structures and other material properties of the transition metals and rare earth metals affect the electrical properties of the dielectric films, the dielectric/silicon and the dielectric/metal gate interfaces, and the resulting device properties. Specific topics include the problems and solutions encountered with high-k material thermal stability, defect density, and poor initial interface with silicon substrate. The text also addresses the essence of thin film deposition, etching, and process integration of high-k materials in an actual CMOS process. Fascinating in both content and approach, Nano-CMOS Gate Dielectric Engineering explains all of the necessary physics in a highly readable manner and supplements this with numerous intuitive illustrations and tables. Covering almost every aspect of high-k gate dielectric engineering for nano-CMOS technology, this is a perfect reference book for graduate students needing a better understanding of developing technology as well as researchers and engineers needing to get ahead in microelectronic engineering and materials science.
Emerging Technologies and Circuits contains a set of outstanding papers, keynote and tutorials presented during 3 days at the International Conference On Integrated Circuit Design and Technology (ICICDT) held in June 2008 in Minatec, Grenoble.