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The focus behind this book on wafer bonding is the fast paced changes in the research and development in three-dimensional (3D) integration, temporary bonding and micro-electro-mechanical systems (MEMS) with new functional layers. Written by authors and edited by a team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies. Part I sorts the wafer bonding technologies into four categories: Adhesive and Anodic Bonding; Direct Wafer Bonding; Metal Bonding; and Hybrid Metal/Dielectric Bonding. Part II summarizes the key wafer bonding applications developed recently, that is, 3D integration, MEMS, and temporary bonding, to give readers a taste of the significant applications of wafer bonding technologies. This book is aimed at materials scientists, semiconductor physicists, the semiconductor industry, IT engineers, electrical engineers, and libraries.
Since its invention, the integrated circuit has necessitated new process modules and numerous architectural changes to improve application performances, power consumption, and cost reduction. Silicon CMOS is now well established to offer the integration of several tens of billions of devices on a chip or in a system. At present, there are important challenges in the introduction of heterogeneous co-integration of materials and devices with the silicon CMOS 2D- and 3D-based platforms. New fabrication techniques allowing strong energy and variability efficiency come in as possible players to improve the various figures of merit of fabrication technology. Integrated Nanodevice and Nanosystem Fabrication: Breakthroughs and Alternatives is the second volume in the Pan Stanford Series on Intelligent Nanosystems. The book contains 8 chapters and is divided into two parts, the first of which reports breakthrough materials and techniques such as single ion implantation in silicon and diamond, graphene and 2D materials, nanofabrication using scanning probe microscopes, while the second tackles the scaling and architectural aspects of silicon devices through HiK scaling for nanoCMOS, nanoscale epitaxial growth of group IV semiconductors, design for variability co-optimization in SOI FinFETs, and nanowires for CMOS and diversifications.