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This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs.
Provides the only up-to-date source on the most recent advances in this often complex and fascinating topic. The only book to be entirely devoted to clocking Clocking has become one of the most important topics in the field of digital system design A "must have" book for advanced circuit engineers
The book addresses the need to investigate new approaches to lower energy requirement in multiple application areas and serves as a guide into emerging circuit technologies. It explores revolutionary device concepts, sensors, and associated circuits and architectures that will greatly extend the practical engineering limits of energy-efficient computation. The book responds to the need to develop disruptive new system architecutres, circuit microarchitectures, and attendant device and interconnect technology aimed at achieving the highest level of computational energy efficiency for general purpose computing systems. Features Discusses unique technologies and material only available in specialized journal and conferences Covers emerging applications areas, such as ultra low power communications, emerging bio-electronics, and operation in extreme environments Explores broad circuit operation, ex. analog, RF, memory, and digital circuits Contains practical applications in the engineering field, as well as graduate studies Written by international experts from both academia and industry
As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC) paradigm has emerged as an efficient and scalable infrastructure to handle the communication needs for such multi-core systems. In most existing NoCs, design decisions are made assuming that the NoC operates at the same or lower clock speed as the cores, which slows down the communication system. A major challenge in designing a high speed NoC is the difficulty of distributing a high speed, low power clock across the chip. In this dissertation, we first propose several techniques to address the issue of distributing a high-speed, low power, low jitter clock across the IC. We primarily focus our attention on resonant standing wave oscillators (SWOs), which have recently emerged as a promising technique for high-speed, low power clock generation. In addition, we also present a dynamic programming based approach to synthesize a low jitter, low power buffered H-tree for clock distribution. In the second part of this dissertation, we use these efficient clock distribution schemes to present a novel fast NoC design that relies on source synchronous data transfer over a ring. In our source-synchronous design, the clock and data NoC are routed in parallel yielding a fast, robust design. Architectural simulations on synthetic and real traffic show that our source-synchronous NoC designs can provide significantly lower latency while achieving the same or better bandwidth compared to a state of the art mesh, while consuming lower area. The fact that the our ring-based NoC runs significantly faster than the mesh contributes to these improvements. Moreover, since our proposed NoC designs are fully synchronous, they are very amenable to testing as well. In the last part of this dissertation, we explore an alternate scheme of achieving high-speed on-chip data transfer using sinusoidal signals of different frequencies. The key advantage of our method is the ability to superimpose such sinusoids and thereby effectively send multiple logic values along the same wire in a clock cycle. Experimental results show that for the same throughput as that of a traditional scheme, we require significantly fewer wires. The electronic version of this dissertation is accessible from http://hdl.handle.net/1969.1/149325
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
The problem of clock generation with low jitter becomes much more challenging as wireline transceivers are designed for higher data rates, e.g., 224 Gb/s. This dissertation addresses the clock generation problem and proposes both integer-N and fractional-N phase-locked loop architectures that achieve low jitter with low power consumption. This dissertation consists of two parts. We first introduce an integer-N PLL that incorporates two new techniques. A double-sampling architecture samples both the rising and falling edge of the reference clock, which improves the in-band phase noise by 3 dB. Also, a robust retiming technique is presented to reduce the phase noise of the frequency divider. Fabricated in 28 nm CMOS technology, the 19-GHz prototype achieves an rms jitter of 20.3 fs from 10 kHz to 100 MHz with a spur of -66 dBc, all at a power of 12 mW. Next, we propose a 56-GHz fractional-N PLL targeting 224-Gb/s PAM4 transmitters. The PLL employs a novel current-mode FIR filter to avoid phase and frequency detectors (PFDs) and charge pumps and to suppress the DSM quantization noise with negligible noise folding. To provide a compact solution suited to multi-lane systems, the PLL also incorporates an inductorless divide-by-8 circuit that draws 3.1 mW. Fabricated in 28-nm CMOS technology, the PLL exhibits an rms jitter of 110 fs, consumes 23 mW, and occupies an active area of 0.1 mm2.