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The contributions of a diverse selection of international hardware and software specialists are assimilated in this book's exploration of the development of massively parallel processing (MPP). The emphasis is placed on industrial applications and collaboration with users and suppliers from within the industrial community consolidates the scope of the publication. From a practical point of view, massively parallel data processing is a vital step to further innovation in all areas where large amounts of data must be processed in parallel or in a distributed manner, e.g. fluid dynamics, meteorology, seismics, molecular engineering, image processing, parallel data base processing. MPP technology can make the speed of computation higher and substantially reduce the computational costs. However, to achieve these features, the MPP software has to be developed further to create user-friendly programming systems and to become transparent for present-day computer software. Application of novel electro-optic components and devices is continuing and will be a key for much more general and powerful architectures. Vanishing of communication hardware limitations will result in the elimination of programming bottlenecks in parallel data processing. Standardization of the functional characteristics of a programming model of massively parallel computers will become established. Then efficient programming environments can be developed. The result will be a widespread use of massively parallel processing systems in many areas of application.
Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures. In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.
Today's electronics industry requires new design automation methodologies that allow designers to incorporate high performance integrated circuits into smaller packaging. The aim of this book is to present current and future techniques and algorithms of high performance multichip modules (MCMs) and other packaging methodologies. Innovative technical papers in this book cover design optimization and physical partitioning; global routing/multi-layer assignment; timing-driven interconnection design (timing models, clock and power design); crosstalk, reflection, and simultaneous switching noise minimization; yield optimization; defect area minimization; low-power physical layout; and design methodologies. Two tutorial reviews review some of the most significant algorithms previously developed for the placement/partitioning, and signal integrity issues, respectively. The remaining articles review the trend of prime design automation algorithms to solve the above eight problems which arise in MCMs and other packages.
The process of Integrated Circuits (IC) started its era of VLSI (Very Large Scale Integration) in 1970’s when thousands of transistors were integrated into one single chip. Nowadays we are able to integrate more than a billion transistors on a single chip. However, the term “VLSI” is still being used, though there was some effort to coin a new term ULSI (Ultra-Large Scale Integration) for fine distinctions many years ago. VLSI technology has brought tremendous benefits to our everyday life since its occurrence. VLSI circuits are used everywhere, real applications include microprocessors in a personal computer or workstation, chips in a graphic card, digital camera or camcorder, chips in a cell phone or a portable computing device, and embedded processors in an automobile, et al. VLSI covers many phases of design and fabrication of integrated circuits. For a commercial chip design, it involves system definition, VLSI architecture design and optimization, RTL (register transfer language) coding, (pre- and post-synthesis) simulation and verification, synthesis, place and route, timing analyses and timing closure, and multi-step semiconductor device fabrication including wafer processing, die preparation, IC packaging and testing, et al. As the process technology scales down, hundreds or even thousands of millions of transistors are integrated into one single chip. Hence, more and more complicated systems can be integrated into a single chip, the so-called System-on-chip (SoC), which brings to VLSI engineers ever increasingly challenges to master techniques in various phases of VLSI design. For modern SoC design, practical applications are usually speed hungry. For instance, Ethernet standard has evolved from 10Mbps to 10Gbps. Now the specification for 100Mbps Ethernet is on the way. On the other hand, with the popularity of wireless and portable computing devices, low power consumption has become extremely critical. To meet these contradicting requirements, VLSI designers have to perform optimizations at all levels of design. This book is intended to cover a wide range of VLSI design topics. The book can be roughly partitioned into four parts. Part I is mainly focused on algorithmic level and architectural level VLSI design and optimization for image and video signal processing systems. Part II addresses VLSI design optimizations for cryptography and error correction coding. Part III discusses general SoC design techniques as well as other application-specific VLSI design optimizations. The last part will cover generic nano-scale circuit-level design techniques.
A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints. The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research. The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers. Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks
Content Description #Includes bibliographical references and index.
Computer Systems Organization -- Computer-Communication Networks.
Introduction to Parallel Algorithms and Architectures: Arrays Trees Hypercubes provides an introduction to the expanding field of parallel algorithms and architectures. This book focuses on parallel computation involving the most popular network architectures, namely, arrays, trees, hypercubes, and some closely related networks. Organized into three chapters, this book begins with an overview of the simplest architectures of arrays and trees. This text then presents the structures and relationships between the dominant network architectures, as well as the most efficient parallel algorithms for a wide variety of problems. Other chapters focus on fundamental results and techniques and on rigorous analysis of algorithmic performance. This book discusses as well a hybrid of network architecture based on arrays and trees called the mesh of trees. The final chapter deals with the most important properties of hypercubes. This book is a valuable resource for readers with a general technical background.