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Enables the reader to test an analog circuit that is implemented either in bipolar or MOS technology. Examines the testing and fault diagnosis of analog and analog part of mixed signal circuits. Covers the testing and fault diagnosis of both bipolar and Metal Oxide Semiconductor (MOS) circuits and introduces . Also contains problems that can be used as quiz or homework.
In this book, we study decision trees for fault diagnosis in circuits and switching networks, which are among the most fundamental models for computing Boolean functions. We consider two main cases: when the scheme (circuit or switching network) has the same mode of operation for both calculation and diagnostics, and when the scheme has two modes of operation—normal for calculation and special for diagnostics. In the former case, we get mostly negative results, including superpolynomial lower bounds on the minimum depth of diagnostic decision trees depending on scheme complexity and the NP-hardness of construction diagnostic decision trees. In the latter case, we describe classes of schemes and types of faults for which decision trees can be effectively used to diagnose schemes, when they are transformed into so-called iteration-free schemes. The tools and results discussed in this book help to understand both the possibilities and challenges of using decision trees to diagnose faults in various schemes. The book is useful to specialists both in the field of theoretical and technical diagnostics.It can also be used for the creation of courses for graduate students.
An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References
Architecture Design for Soft Errors provides a comprehensive description of the architectural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem definition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques. There are a number of different ways this book can be read or used in a course: as a complete course on architecture design for soft errors covering the entire book; a short course on architecture design for soft errors; and as a reference book on classical fault-tolerant machines. This book is recommended for practitioners in semi-conductor industry, researchers and developers in computer architecture, advanced graduate seminar courses on soft errors, and (iv) as a reference book for undergraduate courses in computer architecture. - Helps readers build-in fault tolerance to the billions of microchips produced each year, all of which are subject to soft errors - Shows readers how to quantify their soft error reliability - Provides state-of-the-art techniques to protect against soft errors
With the rapid growth of integration scale of VLSI chips and the present need for reliable computers in space exploration, fault diagnosis and fault toleran ce have become more important than before, and hence reveal a lot of interest ing topics which attract many researchers to make a great number of contribu tions to this field. In recent years, many new and significant results have been achieved. A quick scan over the proceedings of the conferences on fault tolerant computing and design automation as well as on testing will convince the reader of that. But unfortunately these achievements have not been entire ly reflected in the textbooks, so that there seems to be a gap for the new researcher who already has the basic knowledge and wants to begin research in this area. As a remedy for this deficiency, this book is intended for begin ners, especially graduate students, as a textbook which will lead them to the frontier of some branches of the fault-tolerant computing field. The first chapter introduces the four-valued logic B4 and its applica tions. In 1966 Roth first proposed this four-valued logic as a technique to generate tests for logical circuits, but this work did not concern the mathe matical basis of B4 itself.
The third edition of Digital Logic Techniques provides a clear and comprehensive treatment of the representation of data, operations on data, combinational logic design, sequential logic, computer architecture, and practical digital circuits. A wealth of exercises and worked examples in each chapter give students valuable experience in applying the concepts and techniques discussed.Beginning with an objective comparison between analogue and digital representation of data, the author presents the Boolean algebra framework for digital electronics, develops combinational logic design from first principles, and presents cellular logic as an alternative structure more relevant than canonical forms to VLSI implementation. He then addresses sequential logic design and develops a strategy for designing finite state machines, giving students a solid foundation for more advanced studies in automata theory.The second half of the book focuses on the digital system as an entity. Here the author examines the implementation of logic systems in programmable hardware, outlines the specification of a system, explores arithmetic processors, and elucidates fault diagnosis. The final chapter examines the electrical properties of logic components, compares the different logic families, and highlights the problems that can arise in constructing practical hardware systems.
Spectral Techniques and Fault Detection focuses on the spectral techniques for the analysis, testing, and design of digital devices. This book discusses the error detection and correction in digital devices. Organized into 10 chapters, this book starts with an overview of the concepts and tools to evaluate the applicability of various spectral approaches and fault-detection techniques to the design. This text then describes the class of generalized Programmable Logic Array configurations called Encoded PLAs. Other chapters consider the two-sided Chrestenson Transform to the analysis of some pattern properties. This book describes as well a certain type of cellular arrays for highly parallel processing, namely, three-dimensional arrays. The final chapter deals with the system design methods that allow and encourage designers to incorporate the necessary distributed error correction throughout any digital system. This book is a valuable resource for graduate students and engineers working in the fields of logic design, spectral techniques, testing, and self-testing of digital devices.
This book provides readers with insight into an alternative approach for enhancing the reliability, security, and low power features of integrated circuit designs, related to transient faults, hardware Trojans, and power consumption. The authors explain how the addition of integrated sensors enables the detection of ionizing particles and how this information can be processed at a high layer. The discussion also includes a variety of applications, such as the detection of hardware Trojans and fault attacks, and how sensors can operate to provide different body bias levels and reduce power costs. Readers can benefit from these sensors-based approaches through designs with fast response time, non-intrusive integration on gate-level and reasonable design costs.