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This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc. The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter plastic optical fiber (POF).
MOS technology has rapidly become the de facto standard for mixed-signal integrated circuit design due to the high levels of integration possible as device geometries shrink to nanometer scales. The reduction in feature size means that the number of transistor and clock speeds have increased significantly. In fact, current day microprocessors contain hundreds of millions of transistors operating at multiple gigahertz. Furthermore, this reduction in feature size also has a significant impact on mixed-signal circuits. Due to the higher levels of integration, the majority of ASICs possesses some analog components. It has now become nearly mandatory to integrate both analog and digital circuits on the same substrate due to cost and power constraints. This book presents some of the newer problems and opportunities offered by the small device geometries and the high levels of integration that is now possible. The aim of this book is to summarize some of the most critical aspects of high-speed analog/RF communications circuits. Attention is focused on the impact of scaling, substrate noise, data converters, RF and wireless communication circuits and wireline communication circuits, including high-speed I/O. Contents: Achieving Analog Accuracy in Nanometer CMOS (M P Flynn et al.); Self-Induced Noise in Integrated Circuits (R Gharpurey & S Naraghi); High-Speed Oversampling Analog-to-Digital Converters (A Gharbiya et al.); Designing LC VCOs Using Capacitive Degeneration Techniques (B Jung & R Harjani); Fully Integrated Frequency Synthesizers: A Tutorial (S T Moon et al.); Recent Advances and Design Trends in CMOS Radio Frequency Integrated Circuits (D J Allstot et al.); Equalizers for High-Speed Serial Links (P K Hanumolu et al.); Low-Power, Parallel Interface with Continuous-Time Adaptive Passive Equalizer and Crosstalk Cancellation (C P Yue et al.). Readership: Technologists, scientists, and engineers in the field of high-speed communication circuits. It can also be used as a textbook for graduate and advanced undergraduate courses.
Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.
An up-to-date, comprehensive guide for advanced electrical engineering studentsand electrical engineers working in the IC and optical industries This book covers the major transimpedance amplifier (TIA) topologies and their circuit implementations for optical receivers. This includes the shunt-feedback TIA, common-base TIA, common-gate TIA, regulated-cascode TIA, distributed-amplifier TIA, nonresistive feedback TIA, current-mode TIA, burst-mode TIA, and analog-receiver TIA. The noise, transimpedance, and other performance parameters of these circuits are analyzed and optimized. Topics of interest include post amplifiers, differential vs. single-ended TIAs, DC input current control, and adaptive transimpedance. The book features real-world examples of TIA circuits for a variety of receivers (direct detection, coherent, burst-mode, etc.) implemented in a broad array of technologies (HBT, BiCMOS, CMOS, etc.). The book begins with an introduction to optical communication systems, signals, and standards. It then moves on to discussions of optical fiber and photodetectors. This discussion includes p-i-n photodetectors; avalanche photodetectors (APD); optically preamplified detectors; integrated detectors, including detectors for silicon photonics; and detectors for phase-modulated signals, including coherent detectors. This is followed by coverage of the optical receiver at the system level: the relationship between noise, sensitivity, optical signal-to-noise ratio (OSNR), and bit-error rate (BER) is explained; receiver impairments, such as intersymbol interference (ISI), are covered. In addition, the author presents TIA specifications and illustrates them with example values from recent product data sheets. The book also includes: Many numerical examples throughout that help make the material more concrete for readers Real-world product examples that show the performance of actual IC designs Chapter summaries that highlight the key points Problems and their solutions for readers who want to practice and deepen their understanding of the material Appendices that cover communication signals, eye diagrams, timing jitter, nonlinearity, adaptive equalizers, decision point control, forward error correction (FEC), and second-order low-pass transfer functions Analysis and Design of Transimpedance Amplifiers for Optical Receivers belongs on the reference shelves of every electrical engineer working in the IC and optical industries. It also can serve as a textbook for upper-level undergraduates and graduate students studying integrated circuit design and optical communication.
Demand for bandwidth in serial links has been increasing as the communications industry demand higher quantity and quality of information. Whereas traditional gigabit per second links has been in bipolar or GaAs, this research aims to push the use of CMOS process technology in such links. Intrinsic gate speed limitations are overcome by parallelizing the data. The on-chip frequency is maintained at a fraction (1/16) of the off-chip data rate. Clocks with carefully controlled phases tapped from a local ring oscillator are driven to a bank of input samplers to convert the serial bit stream into parallel data. Similarly, the overlap of multiple-phased clocks are used to synchronize the multiplexing of the parallel data onto the transmission line. To perform clock/data recovery, data is further oversampled with finer phase separation and passed to digital logic. The digital logic operates upon the samples to detect transitions in the bit stream to track the bit boundaries. This tracking can operate at the cycle rate of the digital logic allowing robustness to systematic phase noise. The challenge lies in the capturing of the high frequency data stream and generating low jitter, accurately spaced clock edges. A test chip is built demonstrating the transmission and recovery of a 4.0-Gb/s bit streams with
Neural network control has been a research hotspot in academic fields due to the strong ability of computation. One of its wildly applied fields is robotics. In recent years, plenty of researchers have devised different types of dynamic neural network (DNN) to address complex control issues in robotics fields in reality. Redundant manipulators are no doubt indispensable devices in industrial production. There are various works on the redundancy resolution of redundant manipulators in performing a given task with the manipulator model information known. However, it becomes knotty for researchers to precisely control redundant manipulators with unknown model to complete a cyclic-motion generation CMG task, to some extent. It is worthwhile to investigate the data-driven scheme and the corresponding novel dynamic neural network (DNN), which exploits learning and control simultaneously. Therefore, it is of great significance to further research the special control features and solve challenging issues to improve control performance from several perspectives, such as accuracy, robustness, and solving speed.
Final program for the CMOSET Fall 2009 conference.
Presenting the cutting-edge results of new device developments and circuit implementations, High-Speed Devices and Circuits with THz Applications covers the recent advancements of nano devices for terahertz (THz) applications and the latest high-speed data rate connectivity technologies from system design to integrated circuit (IC) design, providing relevant standard activities and technical specifications. Featuring the contributions of leading experts from industry and academia, this pivotal work: Discusses THz sensing and imaging devices based on nano devices and materials Describes silicon on insulator (SOI) multigate nanowire field-effect transistors (FETs) Explains the theory underpinning nanoscale nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs), simulation methods, and their results Explores the physics of the silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), as well as commercially available SiGe HBT devices and their applications Details aspects of THz IC design using standard silicon (Si) complementary metal-oxide-semiconductor (CMOS) devices, including experimental setups for measurements, detection methods, and more An essential text for the future of high-frequency engineering, High-Speed Devices and Circuits with THz Applications offers valuable insight into emerging technologies and product possibilities that are attractive in terms of mass production and compatibility with current manufacturing facilities.