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In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work.
More and more chips are being designed with both analog and digital circuitry next to each other, which makes testing analog circuitry even more challenging. This comprehensive guide reviews all the potential testing options, helping designers, engineers, CAD developers, and researchers choose the most cost-effective, accurate solutions for both mixed-signal and analog-only testing.
Abstract: "Several manufacturing challenges have accompanied the explosive growth in the scale of integration for VLSI circuits. One of these is the increased difficulty of generating manufacturing test sets, which has resulted from the vast increase in the ratio of the number of transistors to the number of I/O pins. The difficulty of test generation is crucial since it impacts both the resultant product quality and time to market, both of which continue to gain importance in the present day semiconductor industry. Design for testability (DFT) techniques can be used to offset this difficulty. The mechanics of such techniques are well understood. DFT techniques are also known to increase other manufacturing costs and to decrease performance. Thus the relevant issue facing designers is not how to use DFT, but rather if such techniques should be applied. The correct decision is a matter of economics. Integrated circuit (IC) designers must balance manufacturing costs, performance, time to market, and product quality concerns. Achieving the desired balance requires the ability to quantify trade-offs in the different manufacturing costs which various DFT techniques would affect. Unfortunately, test generation cost is among the least predictable of these affected costs, even though the principal reason that DFT techniques are often applied is to reduce the difficulty of test generation. Furthermore, there does not exist a complete understanding of which circuit attributes influence the difficulty of test generation. In this thesis, a model is developed which predicts the difficulty of automatic test generation for non-scan sequential circuits. This model is based on a newly recognized circuit attribute, termed density of encoding, which differs from those notions which have been used to describe this difficulty in the past. This thesis also discusses how the concept of the density of encoding can be applied to devise more powerful sequential automatic test pattern generation algorithms, more efficient DFT techniques, and more effective synthesis for testability schemes."
IS THE TOPIC ANALOG TESTING AND DIAGNOSIS TIMELY? Yes, indeed it is. Testing and Diagnosis is an important topic and fulfills a vital need for the electronic industry. The testing and diagnosis of digital electronic circuits has been successfuIly developed to the point that it can be automated. Unfortu nately, its development for analog electronic circuits is still in its Stone Age. The engineer's intuition is still the most powerful tool used in the industry! There are two reasons for this. One is that there has been no pressing need from the industry. Analog circuits are usuaIly small in size. Sometimes, the engineer's experience and intuition are sufficient to fulfill the need. The other reason is that there are no breakthrough results from academic re search to provide the industry with critical ideas to develop tools. This is not because of a lack of effort. Both academic and industrial research groups have made major efforts to look into this problem. Unfortunately, the prob lem for analog circuits is fundamentally different from and much more diffi cult than its counterpart for digital circuits. These efforts have led to some important findings, but are still not at the point of being practicaIly useful. However, these situations are now changing. The current trend for the design of VLSI chips is to use analog/digital hybrid circuits, instead of digital circuits from the past. Therefore, even Ix x Preface though the analog circuit may be small, the total circuit under testing is large.
The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.
With the growing complexity of today's integrated circuit designs, engineers have abandoned the use of pure functional test vectors wherever possible, and adopted various DFT solutions to make their designs more test-friendly. The most common DFT approach for digital designs is scan insertion and automatic test pattern generation (ATPG). ATPG is performed based on fault models associated with the design or gates within the design. Traditionally, the most popular model is the stuck-at model. However, as transistor size continues to shrink, new defect mechanisms start to appear that affect the speed of the design, and so can no longer be properly modelled by this model. Consequently, a new fault model called transition-delay fault models is created to allow ATPG to detect at-speed defects. Another model called path-delay fault model is also created for speed-grading/binning and I/0 timing characterization on scan-inserted designs. As part of an ongoing DFT development for PMC-Sierra Inc., a suite of automation flows have been implemented to perform AC-Scan ATPG. This includes transition-delay ATPG with DC top-up ATPG for delay defect detection, path-delay ATPG for speed-grading/binning and I/0 timing characterization, and AC-scan ATPG for RAM interfaces with multi-load algorithm.