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Both schemes allow routing decisions to be made dynamically at the nodes along the message path, based on output channel contention among the messages at that node. Virtual cut-through routing, which combines features of circuit and packet switching methodologies, is used. In this paper we develope [sic] approximate analytical models for these two implementations of adaptive routing based on birth and death queueing process; extensive simulation experiments are performed to validate the models as well as to evaluate the performance of the adaptive routing schemes with respect to the deterministic routing."
This thesis proposes two new limited global- information-based fault-tolerant routing algorithms for k-ary n-cubes, namely the unsafety vectors algorithm and the probability vectors algorithm. While the first algorithm uses a deterministic approach, which has been widely employed by other existing algorithms, the second algorithm is the first that uses probability-based fault-tolerant routing. These two algorithms have two important advantages over those already existing in the relevant literature. Both algorithms ensure fault- tolerance under relaxed assumptions, regarding the number of faulty nodes and their locations in the network. Furthermore, the new algorithms are more general in that they can easily be adapted to different topologies, including those that belong to the family of k-ary n-cubes.
This volume contains revised versions of the 23 regular papers presented at the First International Workshop on Parallel Computer Routing and Communication (PCRCW '94), held in Seattle, Washington in May 1994. Routing for parallel computer communication has recently experienced almost explosive activity: ever increasing processor speeds are placing greater demands on interprocessor communication, while technological advances offer new capabilities to respond to those demands. The contributions from industry and academia cover all areas, from details of hardware design to proofs of theoretical results. There are also many papers dealing with the performance of various adaptive routing schemes, new network topologies, network interfaces, and fault-tolerant issues.
Clusters of workstations/PCs connected by o?-the-shelf networks have become popular as a platform for cost-e?ective parallel computing. Hardware and so- ware technological advances have made this network-based parallel computing platform feasible. A large number of research groups from academia and industry are working to enhance the capabilities of such a platform, thereby improving its cost-e?ectiveness and usability. These developments are facilitating the mig- tion of many existing applications as well as the development of new applications on this platform. Continuing in the tradition of the two previously successful workshops, this 3rd Workshop on Communication, Architecture and Applications for Netwo- based Parallel Computing (CANPC’99) has brought together researchers and practitioners working in architecture, system software, applications and perf- mance evaluation to discuss state-of-the-art solutions for network-based parallel computing systems. This workshop has become an excellent forum for timely dissemination of ideas and healthy interaction on topics at the cutting edge in cluster computing technology. Each submitted paper underwent a rigorous review process, and was assigned to at least 3 reviewers, including at least 2 program committee members. Each paper received at least 2 reviews, most received 3 and some even had 4 reviews.
This book constitutes the refereed proceedings of the Third International Symposium on Parallel and Distributed Processing and Applications, ISPA 2005, held in Nanjing, China in November 2005. The 90 revised full papers and 19 revised short papers presented together with 3 keynote speeches and 2 tutorials were carefully reviewed and selected from 645 submissions. The papers are organized in topical sections on cluster systems and applications, performance evaluation and measurements, distributed algorithms and systems, fault tolerance and reliability, high-performance computing and architecture, parallel algorithms and systems, network routing and communication algorithms, security algorithms and systems, grid applications and systems, database applications and data mining, distributed processing and architecture, sensor networks and protocols, peer-to-peer algorithms and systems, internet computing and Web technologies, network protocols and switching, and ad hoc and wireless networks.
I wish to welcome all of you to the International Symposium on High Perf- mance Computing 2000 (ISHPC 2000) in the megalopolis of Tokyo. After having two great successes with ISHPC’97 (Fukuoka, November 1997) and ISHPC’99 (Kyoto, May 1999), many people have requested that the symposium would be held in the capital of Japan and we have agreed. I am very pleased to serve as Conference Chair at a time when high p- formance computing (HPC) has a signi?cant in?uence on computer science and technology. In particular, HPC has had and will continue to have a signi?cant - pact on the advanced technologies of the “IT” revolution. The many conferences and symposiums that are held on the subject around the world are an indication of the importance of this area and the interest of the research community. One of the goals of this symposium is to provide a forum for the discussion of all aspects of HPC (from system architecture to real applications) in a more informal and personal fashion. Today we are delighted to have this symposium, which includes excellent invited talks, tutorials and workshops, as well as high quality technical papers.
Foreword -- Foreword to the First Printing -- Preface -- Chapter 1 -- Introduction -- Chapter 2 -- Message Switching Layer -- Chapter 3 -- Deadlock, Livelock, and Starvation -- Chapter 4 -- Routing Algorithms -- Chapter 5 -- CollectiveCommunicationSupport -- Chapter 6 -- Fault-Tolerant Routing -- Chapter 7 -- Network Architectures -- Chapter 8 -- Messaging Layer Software -- Chapter 9 -- Performance Evaluation -- Appendix A -- Formal Definitions for Deadlock Avoidance -- Appendix B -- Acronyms -- References -- Index.