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For next generation MOSFETs, the constant field scaling rule dictates a reduction in the gate oxide thickness among other parameters. Consequently, gate leakage current becomes a serious issue with very thin SiO2 that is conventionally used as gate dielectric since it is the native oxide for Si substrate. This has driven an industry wide search for suitable alternate 'high-k' gate dielectric that has a high value of relative permittivity compared to SiO2 thereby presenting a physically thicker barrier for tunneling carriers while providing a high gate capacitance. Consequently, it is essential to study the properties of these novel materials and the interfaces that they form with the substrate, gate or other dielectrics in a multi-level stack. The main focus of this work is the 1/f noise that is specifically used as a characterization tool to evaluate the performance of high-k MOSFETs. Nevertheless, DC and split C-V characterization are done as well to obtain device performance parameters that are used in the noise analysis. At first, the room temperature 1/f noise characteristics are presented for n- and p-channel poly-Si gated MOSFETs with three different gate dielectrics- HfO2, Al2O3 (top layer)/HfO2 (bottom layer), HfAlOx. The devices had either 1 nm or 4 nm SiO2 interfacial layer, thus presenting an opportunity to understand the effects of interfacial layer thickness on noise and carrier mobility. In the initial study, the analysis of noise is done based on the Unified Flicker Noise Model. Next, a comparative study of 1/f noise behavior is presented for TaSiN (NMOS) and TiN (PMOS) gated MOSFETs with HfO2 gate dielectric and their poly-Si gated counterparts. Additionally, in TaSiN MOSFETs, the effect of the different deposition methods employed for interfacial layer formation on the overall device performance is studied. Finally, the 'Multi-Stack Unified Noise' model (MSUN) is proposed to better model/characterize the 1/f noise in multi-layered high-k MOSFETs. This model takes the non-uniform trap density profile and other physical properties of the constituent gate dielectrics into account. The MSUN model is shown to be in excellent agreement with the experimental data obtained on TaSiN/HfO 2/SiO2 MOSFETs in the 78-350 K range. Additionally, the MSUN model is expressed in terms of surface potential based parameters for inclusion in to the circuit simulators.
The issue of ECS Transactions contains papers presented at the Tenth International Symposium on Silicon Nitride, Silicon Dioxide, and Alternate Emerging Dielectrics held in San Francisco on May 24-29, 2009. The papers address a very wide range of fabrication and characterization techniques, and applications of thin dielectric films in microelectronic and optoelectronic devices. More specific topics addressed by the papers include reliability, interface states, gate oxides, passivation, and dielctric breakdown.
This volume explores and addresses the challenges of high-k gate dielectric materials, one of the major concerns in the evolving semiconductor industry and the International Technology Roadmap for Semiconductors (ITRS). The application of high-k gate dielectric materials is a promising strategy that allows further miniaturization of microelectronic components. This book presents a broad review of SiO2 materials, including a brief historical note of Moore’s law, followed by reliability issues of the SiO2 based MOS transistor. It goes on to discuss the transition of gate dielectrics with an EOT ~ 1 nm and a selection of high-k materials. A review of the various deposition techniques of different high-k films is also discussed. High-k dielectrics theories (quantum tunneling effects and interface engineering theory) and applications of different novel MOSFET structures, like tunneling FET, are also covered in this book. The volume also looks at the important issues in the future of CMOS technology and presents an analysis of interface charge densities with the high-k material tantalum pentoxide. The issue of CMOS VLSI technology with the high-k gate dielectric materials is covered as is the advanced MOSFET structure, with its working structure and modeling. This timely volume will prove to be a valuable resource on both the fundamentals and the successful integration of high-k dielectric materials in future IC technology.
Offering thorough coverage of atomic layer deposition (ALD), this book moves from basic chemistry of ALD and modeling of processes to examine ALD in memory, logic devices and machines. Reviews history, operating principles and ALD processes for each device.
"Following their first observation in 1984, random telegraph signals (RTSs) were initially a purely scientific tool to study fundamental aspects of defects in semiconductor devices. As semiconductor devices move to the nanoscale however, RTSs have become an issue of major concern to the semiconductor industry, both in development of current technology, such as memory devices and logic circuits, as well as in future semiconductor devices beyond the silicon roadmap, such as nanowire, TFET and carbon nanotube-based devices. It has become clear that the reliability of state-of-the-art and future CMOS technology nodes is dominated by RTS and single trap phenomena, and so its understanding is of vital importance for the modelling and simulation of the operation and the expected lifetime of CMOS devices and circuits. It is the aim of this book to provide a comprehensive and up-to-date review of one of the most challenging issues facing the semiconductor industry, from the fundamentals of RTSs to applied technology."--Prové de l'editor.
Fundamentals of III-V Semiconductor MOSFETs presents the fundamentals and current status of research of compound semiconductor metal-oxide-semiconductor field-effect transistors (MOSFETs) that are envisioned as a future replacement of silicon in digital circuits. The material covered begins with a review of specific properties of III-V semiconductors and available technologies making them attractive to MOSFET technology, such as band-engineered heterostructures, effect of strain, nanoscale control during epitaxial growth. Due to the lack of thermodynamically stable native oxides on III-V's (such as SiO2 on Si), high-k oxides are the natural choice of dielectrics for III-V MOSFETs. The key challenge of the III-V MOSFET technology is a high-quality, thermodynamically stable gate dielectric that passivates the interface states, similar to SiO2 on Si. Several chapters give a detailed description of materials science and electronic behavior of various dielectrics and related interfaces, as well as physics of fabricated devices and MOSFET fabrication technologies. Topics also include recent progress and understanding of various materials systems; specific issues for electrical measurement of gate stacks and FETs with low and wide bandgap channels and high interface trap density; possible paths of integration of different semiconductor materials on Si platform.
This is an introduction to noise, describing fundamental noise sources and basic circuit analysis, discussing characterization of low-frequency noise and offering practical advice that bridges concepts of noise theory and modelling, characterization, CMOS technology and circuits. The text offers the latest research, reviewing the most recent publications and conference presentations. The book concludes with an introduction to noise in analog/RF circuits and describes how low-frequency noise can affect these circuits.
Most of the recent texts on compact modeling are limited to a particular class of semiconductor devices and do not provide comprehensive coverage of the field. Having a single comprehensive reference for the compact models of most commonly used semiconductor devices (both active and passive) represents a significant advantage for the reader. Indeed, several kinds of semiconductor devices are routinely encountered in a single IC design or in a single modeling support group. Compact Modeling includes mostly the material that after several years of IC design applications has been found both theoretically sound and practically significant. Assigning the individual chapters to the groups responsible for the definitive work on the subject assures the highest possible degree of expertise on each of the covered models.