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Abstract: "Multi-level simulation with a dynamic model level selection mechanism is a technique for increasing simulation efficiency. Implementation considerations dictate a pessimistic dynamic model selection mechanism which could result in longer execution times than a normal simulation of a flattened logic network. Our equivalence class concept lessens the impact of the pessimistic selection mechanism by detecting currently dormant logic blocks with respect to an input transition."
Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the ?Degradation Delay Model?, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s)
Abstract: "Unavoidable statistical fluctuations of the fabrication process parameters result in statistical variations of the path delays. The estimation of the path delay probability density function (pdf) is necessary in certain applications such as statistical design centering. Event queue re-evaluation is a scheme to allow computationally inexpensive simulations of different process conditions for a given input test vector by incrementally updating the results from a nominal simulation run. Since logic behavior is not considered, the event queue re-evaluation scheme is not valid when process conditions cause different event orderings.
AND BACKGROUND 1. 1 CAD, Specification and Simulation Computer Aided Design (CAD) is today a widely used expression referring to the study of ways in which computers can be used to expedite the design process. This can include the design of physical systems, architectural environments, manufacturing processes, and many other areas. This book concentrates on one area of CAD: the design of computer systems. Within this area, it focusses on just two aspects of computer design, the specification and the simulation of digital systems. VLSI design requires support in many other CAD areas, induding automatic layout. IC fabrication analysis, test generation, and others. The problem of specification is unique, however, in that it i!> often the first one encountered in large chip designs, and one that is unlikely ever to be completely automated. This is true because until a design's objectives are specified in a machine-readable form, there is no way for other CAD tools to verify that the target system meets them. And unless the specifications can be simulated, it is unlikely that designers will have confidence in them, since specifications are potentially erroneous themselves. (In this context the term target system refers to the hardware and/or software that will ultimately be fabricated. ) On the other hand, since the functionality of a VLSI chip is ultimately determined by its layout geometry, one might question the need for CAD tools that work with areas other than layout.
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CMOS chips are becoming increasingly important in computer circuitry. They have been widely used during the past decade, and they will continue to grow in popularity in those application areas that demand high performance. Challenging the prevailing opinion that circuit simulation can reveal all problems in CMOS circuits, Masakazu Shoji maintains that simulation cannot completely remove the often costly errors that occur in circuit design. To address the failure modes of these circuits more fully, he presents a new approach to CMOS circuit design based on his systematizing of circuit design error and his unique theory of CMOS digital circuit operation. In analyzing CMOS digital circuits, the author focuses not on effects originating from the characteristics of the device (MOSFET) but on those arising from their connection. This emphasis allows him to formulate a powerful but ultimately simple theory explaining the effects of connectivity by using a concept of the states of the circuits, called microstates. Shoji introduces microstate sequence diagrams that describe the state changes (or the circuit connectivity changes), and he uses his microstate theory to analyze many of the conventional CMOS digital circuits. These analyses are practically all in closed-form, and they provide easy physical interpretation of the circuit's working mechanisms, the parametric dependence of performance, and the circuit's failure modes. Originally published in 1992. The Princeton Legacy Library uses the latest print-on-demand technology to again make available previously out-of-print books from the distinguished backlist of Princeton University Press. These editions preserve the original texts of these important books while presenting them in durable paperback and hardcover editions. The goal of the Princeton Legacy Library is to vastly increase access to the rich scholarly heritage found in the thousands of books published by Princeton University Press since its founding in 1905.
Mixed-Mode Simulation and Analog Multilevel Simulation addresses the problems of simulating entire mixed analog/digital systems in the time-domain. A complete hierarchy of modeling and simulation methods for analog and digital circuits is described. Mixed-Mode Simulation and Analog Multilevel Simulation also provides a chronology of the research in the field of mixed-mode simulation and analog multilevel simulation over the last ten to fifteen years. In addition, it provides enough information to the reader so that a prototype mixed-mode simulator could be developed using the algorithms in this book. Mixed-Mode Simulation and Analog Multilevel Simulation can also be used as documentation for the SPLICE family of mixed-mode programs as they are based on the algorithms and techniques described in this book.