Download Free Timing Verification By Formal Signal Interaction Modeling In A Multi Level Timing Simulator Book in PDF and EPUB Free Download. You can read online Timing Verification By Formal Signal Interaction Modeling In A Multi Level Timing Simulator and write the review.

Abstract: "Modern VLSI designs are characterized by tight timing constraints, increased importance of the parasitics and large correlated variations in the process-dependent parameters. This work is focused on the development of new techniques to verify the timing behavior of the circuit under these process-dependent parameter variations and predict the location and size of the possible delay faults. The formal modeling of signal interaction presented in this thesis has allowed the formulation of conservative conditions on the validity of circuit macromodels. These conditions form the basis of efficient and accurate algorithms for multi-level simulation including dynamic level selection, fast statistical timing simulation and delay fault detection."
Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
The quest for higher performance digital systems for applications such as gen eral purpose computing, signal/image processing, and telecommunications and an increasing cost consciousness have led to a major thrust for high speed VLSI systems implemented in inexpensive and widely available technologies such as CMOS. This monograph, based on the first author's doctoral dissertation, con centrates on the technique of wave pipelining as one method toward achieving this goal. The primary focus of this monograph is to provide a coherent pre sentation of the theory of wave pipelined operation of digital circuits and to discuss practical design techniques for the realization of wave pipelined circuits in the CMOS technology. Wave pipelining can be applied to a variety of cir cuits for increased performance. For example, many architectures that support systolic computation lend themselves to wave pipelined realization. Also, the wave pipeline design methodology emphasizes the role of controlled clock skew in extracting enhanced performance from circuits that are not deeply pipelined. Wave pipelining (also known as maximal rate pipelining) is a timing method ology used in digital systems to increase the number of effective pipeline stages without increasing the number of physical registers in the pipeline. Using this technique, new data is applied to the inputs of a combinational logic block be fore the outputs due to previous inputs are available thus effectively pipelining the combinational logic and maximizing the utilization of the logic.
BiCMOS Technology and Applications, Second Edition provides a synthesis of available knowledge about the combination of bipolar and MOS transistors in a common integrated circuit - BiCMOS. In this new edition all chapters have been updated and completely new chapters on emerging topics have been added. In addition, BiCMOS Technology and Applications, Second Edition provides the reader with a knowledge of either CMOS or Bipolar technology/design a reference with which they can make educated decisions regarding the viability of BiCMOS in their own application. BiCMOS Technology and Applications, Second Edition is vital reading for practicing integrated circuit engineers as well as technical managers trying to evaluate business issues related to BiCMOS. As a textbook, this book is also appropriate at the graduate level for a special topics course in BiCMOS. A general knowledge in device physics, processing and circuit design is assumed. Given the division of the book, it lends itself well to a two-part course; one on technology and one on design. This will provide advanced students with a good understanding of tradeoffs between bipolar and MOS devices and circuits.
This volume is the first complete overview of VLSI design methods that use statistical techniques for dealing with the random phenomena that are inherent in all VLSI manufacturing processes. VLSI design today cannot be performed without taking into account economic-related issues such as yield, cost and performance oriented tradeoffs. The book includes practical methods relevant to real life applications. It contains edited papers by top industrial and academic specialists in the field. These papers describe all three categories of CAD tools employed for statistical design: IC performance optimization tools, process simulation tools and tools for characterization of process fluctuations. In each category both practical approaches and more theoretical approaches are presented.
This is a new text book introducing VHDL hardware description language & top down system design. The book emphasizes the difference between regular high level computer language & VHDL. As soon as VHDL constructs are introduced, readers are guided through a progressive series of examples to show the modeling techniques. More complex examples are introduced in later chapters to show the top down system design methodology. Distinguished features include: 89 examples of VHDL programming examples. Examples are available on diskette upon request. Exercises & problems at the end of chapters. Answer book available. MSI & SSI logic circuits modeling. Timing modeling & accuracy discussion. Corresponding behavioral, dataflow & structural models. Models of finite impulse response filter (FIR). Models of fast Fourier transform (FFT) hardware. Models of a simple 4-bit computer. Models of a SCSI communication protocol. Models of erasable programmable logic devices (EPLD). 1992 VHDL update in Appendix. DIGITAL SYSTEM DESIGN USING VHDL (ISBN 1-882819-00-4) $29.00. Digital System Design Using VHDL Examples Diskette (ISBN 1-882819-01-2) $15.00. To order: CorralTek, P.O. Box 2616, Salinas, CA 93902. Tel/FAX: (408) 484-1726.