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Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2 thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.
The path of down-scaling traditional MOSFET is reaching its technological, economic and, most importantly, fundamental physical limits. Before the dead-end of the roadmap, it is imperative to conduct a broad research to find alternative materials and new architectures to the current technology for the MOSFET devices. Beyond silicon electronic materials like group III-V heterostructure, ferroelectric material, carbon nanotubes (CNTs), and other nanowire-based designs are in development to become the core technology for non-classical CMOS structures. Field effect transistors (FETs) in general have made unprecedented progress in the last few decades by down-scaling device dimensions and power supply level leading to extremely high numbers of devices in a single chip. High density integrated circuits are now facing major challenges related to power management and heat dissipation due to excessive leakage, mainly due to subthreshold conduction. Over the years, planar MOSFET dimensional reduction was the only process followed by the semiconductor industry to improve device performance and to reduce the power supply. Further scaling increases short-channel-effect (SCE), and off-state current makes it difficult for the industry to follow the well-known Moore’s Law with bulk devices. Therefore, scaling planar MOSFET is no longer considered as a feasible solution to extend this law. The down-scaling of metal-oxide-semiconductor field effect transistors (MOSFETs) leads to severe short-channel-effects and power leakage at large-scale integrated circuits (LSIs). The device, which is governed by the thermionic emission of the carriers injected from the source to the channel region, has set a limitation of the subthreshold swing (S) of 60 mV/decade at room temperature. Devices with ‘S’ below this limit is highly desirable to reduce the power consumption and maintaining a high Ion/Ioff current ratio. Therefore, the future of semiconductor industry hangs on new architectures, new materials or even new physics to govern the flow of carriers in new switches. As the subthreshold swing is increasing at every technology node, new structures using SOI, multi-gate, nanowire approach, and new channel materials such as III–V semiconductor have not satisfied the targeted values of subthreshold swing. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic emission limit of 60 mV/decade. This value was unbreakable by the new structure (SOI FinFET). On the other hand, most of the preview proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for sub-60 mV/decade designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This dissertation also proposes a novel design that exploits the concept of negative capacitance. The new field-effect-transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field effect-transistor (SOFFET). This proposal is a promising methodology for future ultra low-power applications because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers a subthreshold swing significantly lower than 60 mV/decade and reduced threshold voltage to form a conducting channel. The proposed SOFFET design, which utilizes the negative capacitance of a ferroelectric insulator in the body-stack, is completely different from the FeFET and NCFET designs. In addition to having the NC effect, the proposed device will have all the advantages of an SOI device. Body-stack that we are intending in this research has many advantages over the gate-stack. First, it is more compatible with the existing processes. Second, the gate and the working area of the proposed SOFFET is like the planar MOSFET. Third, the complexity and ferroelectric material interferences are shifted to the body of the device from the gate and the working area. The proposed structure offers better scalability and superior constructability because of the high-dielectric buried insulator. Here we are providing a very simplified model for the structure. Silicon-on-ferroelectric leads to several advantages including low off-state current and shift in the threshold voltage with the decrease of the ferroelectric material thickness. Moreover, having an insulator in the body of the device increases the controllability over the channel, which leads to the reduction in the short-channel-effect (SCE). The proposed SOFFET offers low value of subthreshold swing (S) leading to better performance in the on-state. The off-state current is directly related to S. So, the off-state current is also minimum in the proposed structure.
Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.
The scaling of silicon field effect transistors (FETs) has progressed exponentially following Moore's law, and is nearing fundamental limitations related to the materials and physics of the devices. Alternative materials are required to overcome these limitations leading to increasing interest in two dimensional (2D) materials, and transition metal dichalcogenides (TMDs) in particular, due to their atomically thin nature which provides an advantage in scalability. Numerous investigations within the literature have explored various applications of these materials and assessed their viability as a replacement for silicon FETs. This dissertation focuses on several applications of 2D FETs as well as an exploration into one of the most promising methods to improve their performance. Neuromorphic computing is an alternative method to standard computing architectures that operates similarly to a biological nervous system. These systems are composed of neurons and operate based on pulses called action potentials. The neurons communicate with each other through connections called synapses which release neurotransmitters in response to incoming action potentials. By exploiting hysteresis effects in MoS2 transistors, it is found that applied gate pulses can be used to directly model several key behaviors governing biological neurotransmitter release. This enables the FET to function as a synaptic device which mimics the biological behavior more completely than in typical neuromorphic devices. In particular, the gate pulse polarity, the number of pulses, and the pulse magnitude are used to mimic the bipolar, quantal, and stochastic nature of neurotransmitter release. Additionally, it is found that the long trap state decay time can be used as an analog to long-term potentiation which is a process responsible for biological learning and memory. Radiation resistance is an important factor for electronics used in certain space and nuclear applications. Numerous studies have investigated the effects of high energy radiation on 2D electronics. However, these studies typically do not account for the electrical effects of radiation damage to the gate dielectric which also contributes to the total change in device characteristics. A novel experimental setup which uses four samples and takes advantage of the unique properties of 2D materials can eliminate this factor which may obscure the radiation effects on the 2D material itself. The four samples are an unirradiated control sample, a sample where both the flakes and substrate are irradiated, a sample where only the substrate is irradiated, and a sample where only the flakes are irradiated. Using this experimental configuration, it is found that upon exposure to He+ ion radiation at a fluence of 1015 ions/cm2, damage to the electrical characteristics of MoS2 FETs with on a 50 nm Al2O3 gate dielectric is mostly induced by damage to the flakes themselves and that oxide damage has a minor but nonzero effect. Similar results of lesser magnitude are found for devices irradiated with protons at a fluence of 1.26 x 1016 ions/cm2. However, in both cases the devices are able to maintain high ON currents and ON/OFF ratios. The main limiting factor preventing the fabrication of high-quality contacts to 2D materials is Schottky barrier formation due to Fermi level pinning. In conventional silicon FETs, heavily doped regions under the contacts are used to reduce the contact resistance. However, substitutional doping in 2D FETs is impractical due to high-temperature requirements. A promising alternative is surface charge transfer doping (SCTD). A comprehensive experimental study supported with Sentaurus TCAD simulations is used to isolate the thickness dependence of surface doping performed through oxygen plasma exposure. It is found that the plasma produced damage for thin flakes, and that as the flake thickness is increased, the desired threshold voltage shift decreases and the minimum OFF state current increases. Sentaurus simulations show that this is caused by a failure of the doping charge to influence the 2D semiconductor near the back-gate due to the increased distance between them. It is also shown that leaving an undoped region in the channel produces the desired improved contact performance while preventing the excessive threshold voltage shifts produced by high levels of uniform doping. Additionally, Sentaurus simulations are used to extract the thickness trends of this extension doping. Finally, the combined experimental and simulation results are used to determine the material and doping charge requirements for effective use of SCTD for improved device performance.
Ferroelectricity in Doped Hafnium Oxide: Materials, Properties and Devices covers all aspects relating to the structural and electrical properties of HfO2 and its implementation into semiconductor devices, including a comparison to standard ferroelectric materials. The ferroelectric and field-induced ferroelectric properties of HfO2-based films are considered promising for various applications, including non-volatile memories, negative capacitance field-effect-transistors, energy storage, harvesting, and solid-state cooling. Fundamentals of ferroelectric and piezoelectric properties, HfO2 processes, and the impact of dopants on ferroelectric properties are also extensively discussed in the book, along with phase transition, switching kinetics, epitaxial growth, thickness scaling, and more. Additional chapters consider the modeling of ferroelectric phase transformation, structural characterization, and the differences and similarities between HFO2 and standard ferroelectric materials. Finally, HfO2 based devices are summarized. Explores all aspects of the structural and electrical properties of HfO2, including processes, modelling and implementation into semiconductor devices Considers potential applications including FeCaps, FeFETs, NCFETs, FTJs and more Provides comparison of an emerging ferroelectric material to conventional ferroelectric materials with insights to the problems of downscaling that conventional ferroelectrics face
Crystalline semiconductors in the form of thin films are crucial materials for many modern, advanced technologies in fields such as microelectronics, optoelectronics, display technology, and photovoltaic technology. Crystalline semiconductors can be produced at surprisingly low temperatures (as low as 120C) by crystallization of amorphous semicon
This book presents the fundamentals of novel gate dielectrics that are being introduced into semiconductor manufacturing to ensure the continuous scaling of CMOS devices. As this is a rapidly evolving field of research we choose to focus on the materials that determine the performance of device applications. Most of these materials are transition metal oxides. Ironically, the d-orbitals responsible for the high dielectric constant cause severe integration difficulties, thus intrinsically limiting high-k dielectrics. Though new in the electronics industry many of these materials are well-known in the field of ceramics, and we describe this unique connection. The complexity of the structure-property relations in TM oxides requires the use of state-of-the-art first-principles calculations. Several chapters give a detailed description of the modern theory of polarization, and heterojunction band discontinuity within the framework of the density functional theory. Experimental methods include oxide melt solution calorimetry and differential scanning calorimetry, Raman scattering and other optical characterization techniques, transmission electron microscopy, and X-ray photoelectron spectroscopy. Many of the problems encountered in the world of CMOS are also relevant for other semiconductors such as GaAs. A comprehensive review of recent developments in this field is thus also given.
Ferroelectric materials have been and still are widely used in many applications, that have moved from sonar towards breakthrough technologies such as memories or optical devices. This book is a part of a four volume collection (covering material aspects, physical effects, characterization and modeling, and applications) and focuses on the application of ferroelectric devices to innovative systems. In particular, the use of these materials as varying capacitors, gyroscope, acoustics sensors and actuators, microgenerators and memory devices will be exposed, providing an up-to-date review of recent scientific findings and recent advances in the field of ferroelectric devices.
Sensors and Microsystems contains a selection of papers presented at the 14th Italian conference on sensors and microsystems. It provides a unique perspective on the research and development of sensors, microsystems and related technologies in Italy. The scientific values of the papers also offers an invaluable source to analyists intending to survey the Italian situation about sensors and microsystems. In an interdisciplinary approachm many aspects of the disciplines are covered, ranging from materials science, chemistry, applied physics, electronic engineering and biotechnologies. Further details of the conference and its full program at the website http://www.microelectronicsevents.com/AISEM