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Over the last few decades, chip performance has increased steadily due to continuous and aggressive technology scaling. However, it leaves chips quite vulnerable to several issues at the same time. High power densities in some particular areas spread across a chip might result in hotspots and thermal gradients, and these can lead to permanent damage to the chip and also can reduce the reliability of the entire system using the chip. As a result, a large number of dynamic thermal management (DTM) solutions have been proposed in recent years for use in multi-core architectures, and accurate temperature information over the entire chip area has become indispensable especially for fine-grain DTM solutions. Naturally, on-chip thermal sensors came to play an important role in providing accurate information on the thermal distribution of a chip, but there still remain some issues regarding the allocation of on-chip thermal sensors. Due to power, die area, and routing issues, it is preferable to limit the total number of on-chip thermal sensors on a die. Their placement also needs to be considered carefully in order to increase the accuracy of full-chip thermal profile reconstruction, especially when just a small number of thermal sensors can be deployed. In addition, it would be preferable to have some way to improve the reading accuracy of low power, small-sized on-chip thermal sensors that usually tend to have very limited accuracy in temperature readings. In this work, an issue will be firstly addressed regarding how to improve the reading accuracy of a low power, small-sized on-chip thermal sensor such as Ring-Oscillator (RO) based sensors at runtime on a software level. Secondly, a question of how to allocate a proper number of thermal sensors on a die in order to get the accurate full-chip scale temperature information on the run is addressed. Additionally, a temperature-aware routing method for global interconnects to minimize the signal propagation delay and also to reduce the probability of chip failure due to electromigration is presented at the end.
Simulation of computer architectures has made rapid progress recently. The primary application areas are hardware/software performance estimation and optimization as well as functional and timing verification. Recent, innovative technologies such as retargetable simulator generation, dynamic binary translation, or sampling simulation have enabled widespread use of processor and system-on-chip (SoC) simulation tools in the semiconductor and embedded system industries. Simultaneously, processor and SoC simulation is still a very active research area, e.g. what amounts to higher simulation speed, flexibility, and accuracy/speed trade-offs. This book presents and discusses the principle technologies and state-of-the-art in high-level hardware architecture simulation, both at the processor and the system-on-chip level.
Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.
This book contains extended and revised versions of the best papers presented at the 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, held in Florianópolis, Brazil, in October 2009. The 8 papers included in the book together with two keynote talks were carefully reviewed and selected from 27 papers presented at the conference. The papers cover a wide variety of excellence in VLSI technology and advanced research addressing the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of theses systems.
This text is based on the class notes of a VLSI signal processing circuit course series (EEE598) the author developed for the EE department at Arizona State University. The materials are organized into nineteen special topics covering various state-of-the-arts symmetry based VLSI circuit design techniques for basic VLSI circuit elements, circuit modules and systems, where the symmetry principle and methods with inherently low PVT sensitivity are used to design VLSI circuits with superior scalability and performance for various VLSI SOC applications.
This book discusses new techniques for detecting, controlling, and exploiting the impacts of temperature variations on nanoscale circuits and systems. A new sensor system is described that can determine the temperature dependence as well as the operating temperature to improve system reliability. A new method is presented to control a circuit’s temperature dependence by individually tuning pull-up and pull-down networks to their temperature-insensitive operating points. This method extends the range of supply voltages that can be made temperature-insensitive, achieving insensitivity at nominal voltage for the first time.
VLSI 2010 Annual Symposium will present extended versions of the best papers presented in ISVLSI 2010 conference. The areas covered by the papers will include among others: Emerging Trends in VLSI, Nanoelectronics, Molecular, Biological and Quantum Computing. MEMS, VLSI Circuits and Systems, Field-programmable and Reconfigurable Systems, System Level Design, System-on-a-Chip Design, Application-Specific Low Power, VLSI System Design, System Issues in Complexity, Low Power, Heat Dissipation, Power Awareness in VLSI Design, Test and Verification, Mixed-Signal Design and Analysis, Electrical/Packaging Co-Design, Physical Design, Intellectual property creating and sharing.
This handbook offers a comprehensive review of the state-of-the-art research achievements in the field of data centers. Contributions from international, leading researchers and scholars offer topics in cloud computing, virtualization in data centers, energy efficient data centers, and next generation data center architecture. It also comprises current research trends in emerging areas, such as data security, data protection management, and network resource management in data centers. Specific attention is devoted to industry needs associated with the challenges faced by data centers, such as various power, cooling, floor space, and associated environmental health and safety issues, while still working to support growth without disrupting quality of service. The contributions cut across various IT data technology domains as a single source to discuss the interdependencies that need to be supported to enable a virtualized, next-generation, energy efficient, economical, and environmentally friendly data center. This book appeals to a broad spectrum of readers, including server, storage, networking, database, and applications analysts, administrators, and architects. It is intended for those seeking to gain a stronger grasp on data center networks: the fundamental protocol used by the applications and the network, the typical network technologies, and their design aspects. The Handbook of Data Centers is a leading reference on design and implementation for planning, implementing, and operating data center networks.
This book constitutes the thoroughly refereed post-conference proceedings of the Third International Conference on Nano-Networks, Nano-Net, held in Boston, MS, USA, in September 2008. The 17 revised full papers presented together with 5 invited presentations were carefully reviewed and selected. The papers address the whole spectrum of Nano-Networks and spans topis like modeling, simulation, statdards, architectural aspects, novel information and graph theory aspects, device physics and interconnects, nanorobotics as well as nano-biological systems.