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An embedded system is loosely defined as any system that utilizes electronics but is not perceived or used as a general-purpose computer. Traditionally, one or more electronic circuits or microprocessors are literally embedded in the system, either taking up roles that used to be performed by mechanical devices, or providing functionality that is not otherwise possible. The goal of this book is to investigate how formal methods can be applied to the domain of embedded system design. The emphasis is on the specification, representation, validation, and design exploration of such systems from a high-level perspective. The authors review the framework upon which the theories and experiments are based, and through which the formal methods are linked to synthesis and simulation. A formal verification methodology is formulated to verify general properties of the designs and demonstrate that this methodology is efficient in dealing with the problem of complexity and effective in finding bugs. However, manual intervention in the form of abstraction selection and separation of timing and functionality is required. It is conjectured that, for specific properties, efficient algorithms exist for completely automatic formal validations of systems. Synchronous Equivalence: Formal Methods for Embedded Systems presents a brand new formal approach to high-level equivalence analysis. It opens design exploration avenues previously uncharted. It is a work that can stand alone but at the same time is fully compatible with the synthesis and simulation framework described in another book by Kluwer Academic Publishers Hardware-Software Co-Design of Embedded Systems: The POLIS Approach, by Balarin et al. Synchronous Equivalence: Formal Methods for Embedded Systems will be of interest to embedded system designers (automotive electronics, consumer electronics, and telecommunications), micro-controller designers, CAD developers and students, as well as IP providers, architecture platform designers, operating system providers, and designers of VLSI circuits and systems.
Why would you read this preface? As we start thinking what to write here, we wonder who is going to read these words. Fromourperspective–thatofwritersaddressinganaudienceofreaders–you are most likely Willem-Paul de Roever. Willem: our main motivation in putting together this Festschrift is to honor you on the occasion of your retirement. In terms of scienti?c ancestry, you are a father to two of us, and a grandfather to 1 the third , and you have had a profound impact on our formation as computer scientists.Atthepersonallevel,weknowyouasakind-hearted,generousperson. We are grateful to know you in these ways, and hope to have encounters with you in many years to come. AnotherlikelypossibilityisthatyouareCorinneorJojanneke,wifeordau- ter of Willem; the two strong pillars on which so much in his life is founded. You share the honor,respect, and love that went into the writing, as will be ackno- edged by those contributing authors that know you – which are almost all. Also, we would like to thank you for your help in sending us photographs for inclusion in this book, and for your encouragement. The next option is that you are one of the contributing authors. In this case you may wonder why it took us so long to get this work published. After all, wasn’tit“almostdone”alreadyattheretirementeventinJuly2008?Theanswer is twofold: we gave everyone ample time to revise their submissions in line with the recommendations by the referees; and we ourselves took ample time to put everything together. Our hope is that this will be visible in the quality of the ?nal result.
This volume constitutes the refereed post-conference proceedings of the 26th IFIP WG 1.5 International Workshop on Cellular Automata and Discrete Complex Systems, AUTOMATA 2020, held in Stockholm, Sweden, in August 2020. The workshop was held virtually. The 11 full papers presented in this book were carefully reviewed and selected from a total of 21 submissions. The topics of the conference include dynamical, topological, ergodic and algebraic aspects of CA and DCS, algorithmic and complexity issues, emergent properties, formal languages, symbolic dynamics, tilings, models of parallelism and distributed systems, timing schemes, synchronous versus asynchronous models, phenomenological descriptions, scientific modeling, and practical applications.
This book constitutes the refereed proceedings of the 8th International Conference on Concurrency Theory, CONCUR'97. held in Warsaw, Poland, in July 1997. The 24 revised full papers presented were selected by the program committee for inclusion in the volume from a total of 41 high-quality submissions. The volume covers all current topics in the science of concurrency theory and its applications, such as reactive systems, hybrid systems, model checking, partial orders, state charts, program logic calculi, infinite state systems, verification, and others.
This book constitutes the thoroughly refereed post-proceedings of the 10th International Conference on Implementation and Application of Automata, CIAA 2005, held in Sophia Antipolis, France, in June 2005. The 26 revised full papers and 8 revised poster papers presented together with 2 invited contributions were selected from 87 submissions and have gone through two rounds of reviewing and improvement. The topics covered show applications of automata in many fields, including mathematics, linguistics, networks, XML processing, biology and music.
For more than a decade, researchers and engineers have been addressing the problem of the application of formal description techniques to protocol specification, implementation, testing and verification. This book identifies the many successes that have been achieved within the industrial framework and the difficulties encountered in applying theoretical methods to practical situations. Issues discussed include: testing and certification; verification; validation; environments and automated tools; formal specifications; protocol conversion; implementation; specification languages and models. Consideration is also given to the concerns surrounding education available to students and the need to upgrade and develop this through sponsorship of a study of an appropriate curriculum at both undergraduate and graduate levels. It is hoped this publication will stimulate such support and inspire further research in this important arena.
This book gathers outstanding papers presented at the 16th Annual Conference of China Electrotechnical Society, organized by China Electrotechnical Society (CES), held in Beijing, China, from September 24 to 26, 2021. It covers topics such as electrical technology, power systems, electromagnetic emission technology, and electrical equipment. It introduces the innovative solutions that combine ideas from multiple disciplines. The book is very much helpful and useful for the researchers, engineers, practitioners, research students, and interested readers.
This book constitutes the thoroughly refereed post-conference proceedings of the 16th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning, LPAR 2010, which took place in Dakar, Senegal, in April/May 2010. The 27 revised full papers and 9 revised short papers presented together with 1 invited talk were carefully revised and selected from 47 submissions. The papers address all current issues in automated reasoning, computational logic, programming languages and deal with logic programming, logic-based program manipulation, formal methods, and various kinds of AI logics. Subjects covered range from theoretical aspects to various applications such as automata, linear arithmetic, verification, knowledge representation, proof theory, quantified constraints, as well as modal and temporal logics.
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost "push button" manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines.
This book constitutes the proceedings of the 17th International Conference on Theoretical Aspects of Software Engineering, TASE 2023, held in Bristol, UK, July 4–6, 2023. The 19 full papers and 2 short papers included in this book were carefully reviewed and selected from 49 submissions. They cover the following areas: distributed and concurrent systems; cyber-physical systems; embedded and real-time systems; object-oriented systems; quantum computing; formal verification and program semantics; static analysis; formal methods; verification and testing for AI systems; and AI for formal methods.