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Abstract: "Modern VLSI designs are characterized by tight timing constraints, increased importance of the parasitics and large correlated variations in the process-dependent parameters. This work is focused on the development of new techniques to verify the timing behavior of the circuit under these process-dependent parameter variations and predict the location and size of the possible delay faults. The formal modeling of signal interaction presented in this thesis has allowed the formulation of conservative conditions on the validity of circuit macromodels. These conditions form the basis of efficient and accurate algorithms for multi-level simulation including dynamic level selection, fast statistical timing simulation and delay fault detection."
Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
The quest for higher performance digital systems for applications such as gen eral purpose computing, signal/image processing, and telecommunications and an increasing cost consciousness have led to a major thrust for high speed VLSI systems implemented in inexpensive and widely available technologies such as CMOS. This monograph, based on the first author's doctoral dissertation, con centrates on the technique of wave pipelining as one method toward achieving this goal. The primary focus of this monograph is to provide a coherent pre sentation of the theory of wave pipelined operation of digital circuits and to discuss practical design techniques for the realization of wave pipelined circuits in the CMOS technology. Wave pipelining can be applied to a variety of cir cuits for increased performance. For example, many architectures that support systolic computation lend themselves to wave pipelined realization. Also, the wave pipeline design methodology emphasizes the role of controlled clock skew in extracting enhanced performance from circuits that are not deeply pipelined. Wave pipelining (also known as maximal rate pipelining) is a timing method ology used in digital systems to increase the number of effective pipeline stages without increasing the number of physical registers in the pipeline. Using this technique, new data is applied to the inputs of a combinational logic block be fore the outputs due to previous inputs are available thus effectively pipelining the combinational logic and maximizing the utilization of the logic.
Abstract: "A new approach to computing the delay defect and delay fault probabilities has been developed. Using a formal modeling of the signal interactions, a statistical timing simulator capable of detecting delay faults and computing delay defect distributions has been built. This tool produces the delay fault statistics which must be used by delay fault ATPG tools if they are to realistically model process-induced delay failures."
Abstract: "Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths, and large variations in component delays. In such a scenario, it is very important to ensure correct temporal behavior of these circuits, both before and after fabrication. For combinational circuits, it has been shown that it is necessary and sufficient to guarantee that the primitive path delay faults (primitive PDFs) are fault-free to ensure that the circuit operates correctly for some timing constraint T and all larger timing constraints, where primitive PDFs correspond to minimal sets of paths that are singly/jointly non-robustly testable. We show that primitive PDFs determine the stabilization time of the circuit outputs, based on which we develop a feasible method to identify the primitive PDFs in a general multilevel logic circuit. We also develop an approach to determine the maximum circuit delay using this primitive PDF identification mechanism, and prove that this delay is exactly equal to the maximum circuit delay found under the floating mode of operation assumption. Our timing analysis approach provides several advantages over previously reported floating mode timing analyzers: increased accuracy in the presence of component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects; increased efficiency in situations where critical paths need to be re- identified due to component delay speedup (e.g., post-layout delay optimization). We also present a framework for the diagnosis of circuit failures caused by distributed path delay faults. This involves determining the paths/sub-paths and fabrication process parameters that caused the chip failure. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, we propose a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. We apply this metric to estimate the true delay fault coverage of robust test sets."