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A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.
Unfriendly to conventional electronic devices, circuits, and systems, extreme environments represent a serious challenge to designers and mission architects. The first truly comprehensive guide to this specialized field, Extreme Environment Electronics explains the essential aspects of designing and using devices, circuits, and electronic systems intended to operate in extreme environments, including across wide temperature ranges and in radiation-intense scenarios such as space. The Definitive Guide to Extreme Environment Electronics Featuring contributions by some of the world’s foremost experts in extreme environment electronics, the book provides in-depth information on a wide array of topics. It begins by describing the extreme conditions and then delves into a description of suitable semiconductor technologies and the modeling of devices within those technologies. It also discusses reliability issues and failure mechanisms that readers need to be aware of, as well as best practices for the design of these electronics. Continuing beyond just the "paper design" of building blocks, the book rounds out coverage of the design realization process with verification techniques and chapters on electronic packaging for extreme environments. The final set of chapters describes actual chip-level designs for applications in energy and space exploration. Requiring only a basic background in electronics, the book combines theoretical and practical aspects in each self-contained chapter. Appendices supply additional background material. With its broad coverage and depth, and the expertise of the contributing authors, this is an invaluable reference for engineers, scientists, and technical managers, as well as researchers and graduate students. A hands-on resource, it explores what is required to successfully operate electronics in the most demanding conditions.
Space applications, nuclear physics, military operations, medical imaging, and especially electronics (modern silicon processing) are obvious fields in which radiation damage can have serious consequences, i.e., degradation of MOS devices and circuits. Zeroing in on vital aspects of this broad and complex topic, Radiation Effects in Semiconductors addresses the ever-growing need for a clear understanding of radiation effects on semiconductor devices and circuits to combat potential damage it can cause. Features a chapter authored by renowned radiation authority Lawrence T. Clark on Radiation Hardened by Design SRAM Strategies for TID and SEE Mitigation This book analyzes the radiation problem, focusing on the most important aspects required for comprehending the degrading effects observed in semiconductor devices, circuits, and systems when they are irradiated. It explores how radiation interacts with solid materials, providing a detailed analysis of three ways this occurs: Photoelectric effect, Compton effect, and creation of electron-positron pairs. The author explains that the probability of these three effects occurring depends on the energy of the incident photon and the atomic number of the target. The book also discusses the effects that photons can have on matter—in terms of ionization effects and nuclear displacement Written for post-graduate researchers, semiconductor engineers, and nuclear and space engineers with some electronics background, this carefully constructed reference explains how ionizing radiation is creating damage in semiconducting devices and circuits and systems—and how that damage can be avoided in areas such as military/space missions, nuclear applications, plasma damage, and X-ray-based techniques. It features top-notch international experts in industry and academia who address emerging detector technologies, circuit design techniques, new materials, and innovative system approaches.
The path of down-scaling traditional MOSFET is reaching its technological, economic and, most importantly, fundamental physical limits. Before the dead-end of the roadmap, it is imperative to conduct a broad research to find alternative materials and new architectures to the current technology for the MOSFET devices. Beyond silicon electronic materials like group III-V heterostructure, ferroelectric material, carbon nanotubes (CNTs), and other nanowire-based designs are in development to become the core technology for non-classical CMOS structures. Field effect transistors (FETs) in general have made unprecedented progress in the last few decades by down-scaling device dimensions and power supply level leading to extremely high numbers of devices in a single chip. High density integrated circuits are now facing major challenges related to power management and heat dissipation due to excessive leakage, mainly due to subthreshold conduction. Over the years, planar MOSFET dimensional reduction was the only process followed by the semiconductor industry to improve device performance and to reduce the power supply. Further scaling increases short-channel-effect (SCE), and off-state current makes it difficult for the industry to follow the well-known Moore’s Law with bulk devices. Therefore, scaling planar MOSFET is no longer considered as a feasible solution to extend this law. The down-scaling of metal-oxide-semiconductor field effect transistors (MOSFETs) leads to severe short-channel-effects and power leakage at large-scale integrated circuits (LSIs). The device, which is governed by the thermionic emission of the carriers injected from the source to the channel region, has set a limitation of the subthreshold swing (S) of 60 mV/decade at room temperature. Devices with ‘S’ below this limit is highly desirable to reduce the power consumption and maintaining a high Ion/Ioff current ratio. Therefore, the future of semiconductor industry hangs on new architectures, new materials or even new physics to govern the flow of carriers in new switches. As the subthreshold swing is increasing at every technology node, new structures using SOI, multi-gate, nanowire approach, and new channel materials such as III–V semiconductor have not satisfied the targeted values of subthreshold swing. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic emission limit of 60 mV/decade. This value was unbreakable by the new structure (SOI FinFET). On the other hand, most of the preview proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for sub-60 mV/decade designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This dissertation also proposes a novel design that exploits the concept of negative capacitance. The new field-effect-transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field effect-transistor (SOFFET). This proposal is a promising methodology for future ultra low-power applications because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers a subthreshold swing significantly lower than 60 mV/decade and reduced threshold voltage to form a conducting channel. The proposed SOFFET design, which utilizes the negative capacitance of a ferroelectric insulator in the body-stack, is completely different from the FeFET and NCFET designs. In addition to having the NC effect, the proposed device will have all the advantages of an SOI device. Body-stack that we are intending in this research has many advantages over the gate-stack. First, it is more compatible with the existing processes. Second, the gate and the working area of the proposed SOFFET is like the planar MOSFET. Third, the complexity and ferroelectric material interferences are shifted to the body of the device from the gate and the working area. The proposed structure offers better scalability and superior constructability because of the high-dielectric buried insulator. Here we are providing a very simplified model for the structure. Silicon-on-ferroelectric leads to several advantages including low off-state current and shift in the threshold voltage with the decrease of the ferroelectric material thickness. Moreover, having an insulator in the body of the device increases the controllability over the channel, which leads to the reduction in the short-channel-effect (SCE). The proposed SOFFET offers low value of subthreshold swing (S) leading to better performance in the on-state. The off-state current is directly related to S. So, the off-state current is also minimum in the proposed structure.
Silicon on Insulator is more than a technology, more than a job, and more than a venture in microelectronics; it is something different and refreshing in device physics. This book recalls the activity and enthu siasm of our SOl groups. Many contributing students have since then disappeared from the SOl horizon. Some of them believed that SOl was the great love of their scientific lives; others just considered SOl as a fantastic LEGO game for adults. We thank them all for kindly letting us imagine that we were guiding them. This book was very necessary to many people. SOl engineers will certainly be happy: indeed, if the performance of their SOl components is not always outstanding, they can now safely incriminate the relations given in the book rather than their process. Martine, Gunter, and Y. S. Chang can contemplate at last the amount of work they did with the figures. Our SOl accomplices already know how much we borrowed from their expertise and would find it indecent to have their detailed contri butions listed. Jean-Pierre and Dimitris incited the book, while sharing their experience in the reliability of floating bodies. Our families and friends now realize the SOl capability of dielectrically isolating us for about two years in a BOX. Our kids encouraged us to start writing. Our wives definitely gave us the courage to stop writing. They had a hard time fighting the symptoms of a rapidly developing SOl allergy.