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Conventional power converters contain semiconductor devices switching in the tens to hundreds of kilohertz (kHz) range. Extending the switching frequency to the multi-MHz range brings opportunities to reduce the size and weight of power converters as the energy storage requirements decrease. Additionally, MHz-frequency power converters and amplifiers enable new applications such as plasma generators for semiconductor processing equipment, medical sanitation, and CO2 reforming. Despite these promises and opportunities, building efficient power converters at much higher frequencies still poses a significant challenge. In MHz-frequencies, wide bandgap (WBG) semiconductor devices, such as gallium nitride (GaN) and silicon carbide (SiC), have the potential to improve the performance of these systems as they have orders of magnitude lower specific on-resistance compared to silicon (Si) devices. One of the main issues is the soft-switching Coss losses in WBG devices, which have not been previously well-studied and modeled in the literature, and these losses significantly degrade the efficiency of power converters. We present the measurement results and techniques to characterize the Coss losses in wide bandgap devices, as well as discuss the physical root causes of these losses in SiC power devices. In addition to the Coss losses, effectively utilizing SiC MOSFETs poses a challenge, as designing fast transitioning and low loss gate drivers at MHz frequencies is difficult. As a solution, we develop resonant gate drivers that can drive SiC MOSFETs up to 30 MHz while conserving over five times as much gating power compared to available commercial counterparts. Lastly, we utilize these WBG devices in broadband power amplifier demonstrations suitable for radiofrequency (RF) plasma generation applications at 13.56 MHz. To achieve high performance across broadband, we employ various RF circuit techniques including reactance compensation, phase-switched impedance modulation, and power combining. As a result, these amplifiers showcase some of the highest efficiencies published in the literature, including over 90% across a 4 MHz bandwidth for a 300 W system and over 95% efficiency across 4 MHz for a 1 kW system.
This book will introduce various power management integrated circuits (IC) design techniques to build future energy-efficient “green” electronics. The goal is to achieve high efficiency, which is essential to meet consumers’ growing need for longer battery lives. The focus is to study topologies amiable for full on-chip implementation (few external components) in the mainstream CMOS technology, which will reduce the physical size and the manufacturing cost of the devices.
The mass and volume required for power electronics circuitry is a dominant obstacle to the miniaturization and integration of many systems. Likewise, power electronics with greater bandwidth and efficiency are becoming vital in many applications. To realize smaller and highly responsive power electronics at low voltages, this thesis explores devices, circuits, and passives capable of operating efficiently at very high frequencies (VHF, 30-300 MHz). Operation at these frequencies enables reduction of the numerical values and physical size of the passive components that dominate power converters, and enables increased bandwidth and transient performance which is valuable in a multitude of low-voltage and low-power applications. This thesis explores the scaling of magnetic component size with frequency, and it is shown that substantial miniaturization is possible with increased frequencies even considering material and heat transfer limitations. Moreover, the impact of frequency scaling of power converters on magnetic components is investigated for different design criteria. Quantitative examples of magnetics scaling are provided that clearly demonstrate the benefits and opportunities in VHF magnetics design. It is shown to utilize the advantages of frequency scaling on passive component size that system losses and other limitations must be considered. One such area that is examined is semiconductor device requirements, where through a combination of device layout optimization for cascode structures and integrated gate drive designs on a 0.35-um CMOS process, converter performance (i.e., loss and bandwidth) can be significantly improved in the VHF regime. In this thesis a dc-dc converter topology is developed that is suitable for low-voltage power conversion and employs synchronous rectification to improve efficiency. The converter is also comprised of a high-bandwidth and high-switching-frequency inverter topology that can dynamically adjust the output power from one-quarter to full power, while maintaining good efficiency. Furthermore, with its inherent capability of gate-width switching, the inverter can further reduce gating loss by one-half resulting in substantial performance improvements at light load operation. A major contribution of this thesis is the development of a synchronous rectifier operating in the VHF regime. VHF power conversion is especially challenging at low voltages due to poor efficiency resulting from rectification loss. To overcome diode rectification loss, the benefits of synchronous rectification are discussed in the context of a 100MHz class-E resonant rectifier, which results in a 2.5 x overall converter efficiency improvement. The culmination of the developed design techniques in passives, semiconductor devices, and circuit topologies is an experimental prototype of a miniaturized 100MHz, 1W power converter utilizing synchronous rectification.
This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested. With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area.
This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by which sub-threshold and gate oxide leakage currents are generated. The authors present a comprehensive review of state-of-the-art dynamic, static supply and threshold voltage scaling techniques and discuss the pros and cons of supply and threshold voltage scaling techniques.
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
This book provides readers with guidelines for designing integrated multi-MHz-switching converters for input voltages/system supplies up to 50V or higher. Coverage includes converter theory, converter architectures, circuit design, efficiency, sizing of passives, technology aspects, etc. The author discusses new circuit designs, new architectures and new switching concepts, including dead-time control and soft-switching techniques that overcome current limitations of these converters. The discussion includes technology related issues and helps readers to choose the right technology for fast-switching converters. This book discusses benefits and drawbacks in terms of integration, size and cost, efficiency and complexity, and enables readers to make trade-offs in design, given different converter parameters. Describes a study for increasing switching frequencies up to 30 MHz at input voltages up to 50V or higher in the scaling of the size of switching converter passives; Analyzes various buck converter implementations and shows that a preference due to higher efficiency depends on the operating point, on the available switch technologies, and on the implementation of the high-side supply generation; Describes an efficiency model based on a four-phase model, which enables separation of loss causes and loss locations.
High Frequency Communication and Sensing: Traveling-Wave Techniques introduces novel traveling wave circuit techniques to boost the performance of high-speed circuits in standard low-cost production technologies, like complementary metal oxide semiconductor (CMOS). A valuable resource for experienced analog/radio frequency (RF) circuit designers as well as undergraduate-level microelectronics researchers, this book: Explains the basics of high-speed signaling, such as transmission lines, distributed signaling, impedance matching, and other common practical RF background material Promotes a dual-loop coupled traveling wave oscillator topology, the trigger mode distributed wave oscillator, as a high-frequency multiphase signal source Introduces a force-based starter mechanism for dual-loop, even-symmetry, multiphase traveling wave oscillators, presenting a single-loop version as a force mode distributed wave antenna (FMDWA) Describes higher-frequency, passive inductive, and quarter-wave-length-based pumped distributed wave oscillators (PDWOs) Examines phased-array transceiver architectures and front-end circuits in detail, along with distributed oscillator topologies Devotes a chapter to THz sensing, illustrating a unique method of traveling wave frequency multiplication and power combining Discusses various data converter topologies, such as digital-to-analog converters (DACs), analog-to-digital converters (ADCs), and GHz-bandwidth sigma-delta modulators Covers critical circuits including phase rotators and interpolators, phase shifters, phase-locked loops (PLLs), delay-locked loops (DLLs), and more It is a significantly challenging task to generate and distribute high-speed clocks. Multiphase low-speed clocks with sharp transition are proposed to be a better option to accommodate the desired timing resolution. High Frequency Communication and Sensing: Traveling-Wave Techniques provides new horizons in the quest for greater speed and performance.
Gallium nitride (GaN) is an emerging technology that promises to displace silicon MOSFETs in the next generation of power transistors. As silicon approaches its performance limits, GaN devices offer superior conductivity and switching characteristics, allowing designers to greatly reduce system power losses, size, weight, and cost. This timely second edition has been substantially expanded to keep students and practicing power conversion engineers ahead of the learning curve in GaN technology advancements. Acknowledging that GaN transistors are not one-to-one replacements for the current MOSFET technology, this book serves as a practical guide for understanding basic GaN transistor construction, characteristics, and applications. Included are discussions on the fundamental physics of these power semiconductors, layout and other circuit design considerations, as well as specific application examples demonstrating design techniques when employing GaN devices. With higher-frequency switching capabilities, GaN devices offer the chance to increase efficiency in existing applications such as DC–DC conversion, while opening possibilities for new applications including wireless power transfer and envelope tracking. This book is an essential learning tool and reference guide to enable power conversion engineers to design energy-efficient, smaller and more cost-effective products using GaN transistors. Key features: Written by leaders in the power semiconductor field and industry pioneers in GaN power transistor technology and applications. Contains useful discussions on device–circuit interactions, which are highly valuable since the new and high performance GaN power transistors require thoughtfully designed drive/control circuits in order to fully achieve their performance potential. Features practical guidance on formulating specific circuit designs when constructing power conversion systems using GaN transistors – see companion website for further details. A valuable learning resource for professional engineers and systems designers needing to fully understand new devices as well as electrical engineering students.
This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.