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Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF), which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques to improve test generation for path delay faults. The first technique presented in this dissertation avoids testing unnecessary paths by using arithmetic operations. The second technique shows how to compact many faults into a single test application, thus saving valuable test application time. The third technique demonstrates how to generate tests under modern day scan architectures. Experimental results demonstrate the effectiveness of the proposed techniques.
Abstract: "Previous research in the field of path delay fault test generation has concentrated on finding tests which test the paths regardless of component delay values. Coverage of such tests on benchmark circuits has been shown to be poor, so we present a mechanism wherein path delay fault tests are found under the assumption of component delay variations resulting from fabrication process fluctuations. Component delay fault models are built which incorporate fabrication process effects represented in terms of basic device parameter variations. We use a stable time based sensitization approach to get conditions on primary inputs and path delays for which a delay fault is produced at the circuit outputs. A minimal test set is then extracted from these conditions. Results for the ISCAS'89 and Logic synthesis'91 benchmark circuits indicate the feasibility of this approach."
Digital logic circuits must be tested to assure their correct behavior at the desired clock rate. This report describes an algorithm for generating tests for path delay faults; these faults are models of the faulty switching behavior of digital circuits. The path delay fault test generation system developed here is based on an extension to the Sixteen valued Maximized Propagation Lowered Enumeration (SIMPLE) algorithm, which was originally developed for stuck-at faults test generation. The extension of SIMPLE resulted in a powerful path delay fault test generator with the ability to identify nearly every non-robustly detectable fault in a circuit without resorting to the enumeration phase. A parallel implementation of the test generator was developed using the Parallel Virtual Machine (PVM) communication package.
Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.
This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.
Digital logic circuits must be tested to assure their correct behavior at the desired clock rate. This report describes an algorithm for generating tests for path delay faults; these faults are models of the faulty switching behavior of digital circuits. The path delay fault test generation system developed here is based on an extension to the Sixteen valued Maximized Propagation Lowered Enumeration (SIMPLE) algorithm, which was originally developed for stuck-at faults test generation. The extension of SIMPLE resulted in a powerful path delay fault test generator with the ability to identify nearly every non-robustly detectable fault in a circuit without resorting to the enumeration phase. A parallel implementation of the test generator was developed using the Parallel Virtual Machine (PVM) communication package.
This book will introduce new techniques for detecting and diagnosing small-delay defects in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise.
Path selection and generating tests for small delay faults is an important issue in the delay fault area. A novel technique for generating effective vectors for delay defects is the first issue that we have presented in the thesis. The test set achieves high path delay fault coverage to capture small-distributed delay defects and high transition fault coverage to capture gross delay defects. Furthermore, non-robust paths for ATPG are filtered (selected) carefully so that there is a minimum overlap with the already tested robust paths. A relationship between path delay fault model and transition fault model has been observed which helps us reduce the number of non-robust paths considered for test generation. To generate tests for robust and non-robust paths, a deterministic ATPG engine is developed. To deal with small delay faults, we have proposed a new transition fault model called As late As Possible Transition Fault (ALAPTF) Model. The model aims at detecting smaller delays, which will be missed by both the traditional transition fault model and the path delay model. The model makes sure that each transition is launched as late as possible at the fault site, accumulating the small delay defects along its way. Because some transition faults may require multiple paths to be launched, simple path-delay model will miss such faults.