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Parallel Supercomputing in MIMD Architectures is devoted to supercomputing on a wide variety of Multiple-Instruction-Multiple-Data (MIMD)-class parallel machines. This book describes architectural concepts, commercial and research hardware implementations, major programming concepts, algorithmic methods, representative applications, and benefits and drawbacks. Commercial machines described include Connection Machine 5, NCUBE, Butterfly, Meiko, Intel iPSC, iPSC/2 and iWarp, DSP3, Multimax, Sequent, and Teradata. Research machines covered include the J-Machine, PAX, Concert, and ASP. Operating systems, languages, translating sequential programs to parallel, and semiautomatic parallelizing are aspects of MIMD software addressed in Parallel Supercomputing in MIMD Architectures. MIMD issues such as scalability, partitioning, processor utilization, and heterogenous networks are discussed as well.This book is packed with important information and richly illustrated with diagrams and tables, Parallel Supercomputing in MIMD Architectures is an essential reference for computer professionals, program managers, applications system designers, scientists, engineers, and students in the computer sciences.
UNDERSTANDING PARALLEL SUPERCOMPUTING is an exhaustive, applications-oriented survey of the world's largest and fastest computers. Beginning with the evolution of parallel supercomputing technology in recent history, author R. Michael Hord goes on to illustrate architectural concepts and implementations at the very center of today's cutting-edge technology. Topics featured include: technology benefits and drawbacks, software tools and programming languages, major programming concepts, sample parallel programs, algorithmic methods, both SIMD and MIMD architectures. This carefully written text will be of interest to engineers, scientists, and program managers involved in geologic exploration, aircraft design, image processing, weather modeling, operations, research, chemical synthesis, and medical applications. It will also be of practical use to computer specialists.
Parallel Supercomputing in SIMD Architectures is a survey book providing a thorough review of Single-Instruction-Multiple-Data machines, a type of parallel processing computer that has grown to importance in recent years. It was written to describe this technology in depth including the architectural concept, its history, a variety of hardware implementations, major programming languages, algorithmic methods, representative applications, and an assessment of benefits and drawbacks. Although there are numerous books on parallel processing, this is the first volume devoted entirely to the massively parallel machines of the SIMD class. The reader already familiar with low order parallel processing will discover a different philosophy of parallelism--the data parallel paradigm instead of the more familiar program parallel scheme. The contents are organized into nine chapters, rich with illustrations and tables. The first two provide introduction and background covering fundamental concepts and a description of early SIMD computers. Chapters 3 through 8 each address specific machines from the first SIMD supercomputer (Illiac IV) through several contemporary designs to some example research computers. The final chapter provides commentary and lessons learned. Because the test of any technology is what it can do, diverse applications are incorporated throughout, leading step by step to increasingly ambitious examples. The book is intended for a wide range of readers. Computer professionals will find sufficient detail to incorporate much of this material into their own endeavors. Program managers and applications system designers may find the solution to their requirements for high computational performance at an affordable cost. Scientists and engineers will find sufficient processing speed to make interactive simulation a practical adjunct to theory and experiment. Students will find a case study of an emerging and maturing technology. The general reader is afforded the opportunity to appreciate the power of advanced computing and some of the ramifications of this growing capability.
Computer Systems Organization -- Parallel architecture.
Fifteen original contributions from experts in high-speed computation on multi-processor architectures, concurrent programming and parallel algorithms.
THE CONTEXT OF PARALLEL PROCESSING The field of digital computer architecture has grown explosively in the past two decades. Through a steady stream of experimental research, tool-building efforts, and theoretical studies, the design of an instruction-set architecture, once considered an art, has been transformed into one of the most quantitative branches of computer technology. At the same time, better understanding of various forms of concurrency, from standard pipelining to massive parallelism, and invention of architectural structures to support a reasonably efficient and user-friendly programming model for such systems, has allowed hardware performance to continue its exponential growth. This trend is expected to continue in the near future. This explosive growth, linked with the expectation that performance will continue its exponential rise with each new generation of hardware and that (in stark contrast to software) computer hardware will function correctly as soon as it comes off the assembly line, has its down side. It has led to unprecedented hardware complexity and almost intolerable dev- opment costs. The challenge facing current and future computer designers is to institute simplicity where we now have complexity; to use fundamental theories being developed in this area to gain performance and ease-of-use benefits from simpler circuits; to understand the interplay between technological capabilities and limitations, on the one hand, and design decisions based on user and application requirements on the other.
The development of supercomputers has had considerable impact in computational mechanics. This book deals with the application of parallel processing with supercomputers and examines the problems of computational mechanics in a logical way.
Still Image Compression on Parallel Computer Architectures investigates the application of parallel-processing techniques to digital image compression. Digital image compression is used to reduce the number of bits required to store an image in computer memory and/or transmit it over a communication link. Over the past decade advancements in technology have spawned many applications of digital imaging, such as photo videotex, desktop publishing, graphics arts, color facsimile, newspaper wire phototransmission and medical imaging. For many other contemporary applications, such as distributed multimedia systems, rapid transmission of images is necessary. Dollar cost as well as time cost of transmission and storage tend to be directly proportional to the volume of data. Therefore, application of digital image compression techniques becomes necessary to minimize costs. A number of digital image compression algorithms have been developed and standardized. With the success of these algorithms, research effort is now directed towards improving implementation techniques. The Joint Photographic Experts Group (JPEG) and Motion Photographic Experts Group(MPEG) are international organizations which have developed digital image compression standards. Hardware (VLSI chips) which implement the JPEG image compression algorithm are available. Such hardware is specific to image compression only and cannot be used for other image processing applications. A flexible means of implementing digital image compression algorithms is still required. An obvious method of processing different imaging applications on general purpose hardware platforms is to develop software implementations. JPEG uses an 8 × 8 block of image samples as the basic element for compression. These blocks are processed sequentially. There is always the possibility of having similar blocks in a given image. If similar blocks in an image are located, then repeated compression of these blocks is not necessary. By locating similar blocks in the image, the speed of compression can be increased and the size of the compressed image can be reduced. Based on this concept an enhancement to the JPEG algorithm is proposed, called Bock Comparator Technique (BCT). Still Image Compression on Parallel Computer Architectures is designed for advanced students and practitioners of computer science. This comprehensive reference provides a foundation for understanding digital image compression techniques and parallel computer architectures.