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Comprehensive reference on the fundamental principles and basic physics dictating metal–oxide–semiconductor field-effect transistor (MOSFET) operation Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal–oxide–semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs. Additional topics covered include: High-k gate dielectrics and metal gate electrodes for multi-gate MOSFETs, covering gate stack processing and metal gate modification Strain engineering in 3D complementary metal-oxide semiconductors (CMOS) and its scaling impact, and strain engineering in silicon–germanium (SiGe) FinFET and its challenges and future perspectives TCAD simulation of multi-gate MOSFET, covering model calibration and device performance for analog and RF applications Description of the design of an analog amplifier circuit using digital CMOS technology of SCL for ultra-low power VLSI applications Advanced Nanoscale MOSFET Architectures helps readers understand device physics and design of new structures and material compositions, making it an important resource for the researchers and professionals who are carrying out research in the field, along with students in related programs of study.
Fundamentals of Nanoscaled Field Effect Transistors gives comprehensive coverage of the fundamental physical principles and theory behind nanoscale transistors. The specific issues that arise for nanoscale MOSFETs, such as quantum mechanical tunneling and inversion layer quantization, are fully explored. The solutions to these issues, such as high-κ technology, strained-Si technology, alternate devices structures and graphene technology are also given. Some case studies regarding the above issues and solution are also given in the book.
Currently strain engineering is the main technique used to enhance the performance of advanced silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Written from an engineering application standpoint, Strain-Engineered MOSFETs introduces promising strain techniques to fabricate strain-engineered MOSFETs and to methods to assess the applications of these techniques. The book provides the background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOSFETs at nanoscale. This book focuses on recent developments in strain-engineered MOSFETS implemented in high-mobility substrates such as, Ge, SiGe, strained-Si, ultrathin germanium-on-insulator platforms, combined with high-k insulators and metal-gate. It covers the materials aspects, principles, and design of advanced devices, fabrication, and applications. It also presents a full technology computer aided design (TCAD) methodology for strain-engineering in Si-CMOS technology involving data flow from process simulation to process variability simulation via device simulation and generation of SPICE process compact models for manufacturing for yield optimization. Microelectronics fabrication is facing serious challenges due to the introduction of new materials in manufacturing and fundamental limitations of nanoscale devices that result in increasing unpredictability in the characteristics of the devices. The down scaling of CMOS technologies has brought about the increased variability of key parameters affecting the performance of integrated circuits. This book provides a single text that combines coverage of the strain-engineered MOSFETS and their modeling using TCAD, making it a tool for process technology development and the design of strain-engineered MOSFETs.
A new 1/f noise model has been developed for MOSFET devices with high-kappa gate stack. To investigate the impacts of nitridation, MOSFETs with nitrided high-kappa dielectric was used. These devices were provided by Texas Instruments, having four different interfacial layer thicknesses with a stack composition of SiON/HfSiON. The dominant mechanism affecting the noise behavior of these devices was experimentally determined to be correlated number and mobility fluctuation. The impact of remote phonon scattering was investigated in the temperature range of 172K to 300K. It has been observed that the mobility characteristics of these devices were significantly affected by remote phonon scattering. However, the impact of remote phonon scattering was not observed on the flicker noise characteristics. The new model was developed in the frame work of the original Unified Model incorporating two distinct features that distinguish high-kappa gate stacks from SiO2. The new model considers energy and spatial dependence of trap distribution in the dielectric, thus generates a more realistic trap profile. Furthermore, it incorporates the multi layered structure of the gate stack by considering tunneling of carriers through a double step cascaded barrier. The newly developed model is accordingly called MSUN (Multi Stack Unified Noise) Model, named after the original Unified Model. MSUN Model has been successfully verified with data on MOSFETs having four different interfacial layer thicknesses, in the temperature range of 172K to 300K. The model predictions show very good agreement with data in the bias range of moderate to strong inversion. No specific impact due to nitridation was observed on these devices. The model has been successfully transformed into a compact form which is compatible with leading device simulation package used in the industry.
The viability of gate-source/drain underlap as a design parameter, in addition to typical device design parameters like gate length, fin thickness, etc., is investigated in terms of the sensitivity of FinFET performance to the variations of process parameters that influence underlap properties; numerical simulators with UFDG aid this investigation. It is found that while variation in the performance of inverter-based circuits, like the ring oscillator, is reasonable, stability of static random access memory (SRAM) shows wide variation in performance for shorter underlap lengths. Finally, a physics-based compact model for gate tunneling current in DG MOSFETs is developed, verified, and implemented in UFDG to enable reliable prediction of static power consumption in nanoscale FinFET circuits. Model predictions corroborate earlier results that for thinner oxides, present-day silicon oxynitride has to be replaced with high-k dielectrics to control static leakage. However, use of underlap can relax the oxide thickness requirement and hence delay the introduction of high-k dielectrics in FinFET technology.
Analysis and Design of MOSFETs: Modeling, Simulation, and Parameter Extraction is the first book devoted entirely to a broad spectrum of analysis and design issues related to the semiconductor device called metal-oxide semiconductor field-effect transistor (MOSFET). These issues include MOSFET device physics, modeling, numerical simulation, and parameter extraction. The discussion of the application of device simulation to the extraction of MOSFET parameters, such as the threshold voltage, effective channel lengths, and series resistances, is of particular interest to all readers and provides a valuable learning and reference tool for students, researchers and engineers. Analysis and Design of MOSFETs: Modeling, Simulation, and Parameter Extraction, extensively referenced, and containing more than 180 illustrations, is an innovative and integral new book on MOSFETs design technology.
This unique volume assembles the author's scientific and engineering achievements of the past three decades in the areas of (1) semiconductor physics and materials, including topics in deep level defects and band structures, (2) CMOS devices, including the topics in device technology, CMOS device reliability, and nano CMOS device quantum modeling, and (3) Analog Integrated circuit design. It reflects the scientific career of a semiconductor researcher educated in China during the 20th century. The book can be referenced by research scientists, engineers, and graduate students working in the areas of solid state and semiconductor physics and materials, electrical engineering and semiconductor devices, and chemical engineering./a