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This book deals with conformance testing for verification and validation of protocols for communication/distributed computer systems. The reader is introduced to this topic using the Finite State Machine (FSM) model together with a comprehensive review of past and current work. A detailed treatment of graph approaches for vector generation and fault coverage evaluation is presented using examples with real protocols.Qualitative and quantitative measures are introduced to quantify and compare these approaches, inclusive of the length of the generated test sequence and fault detection capabilities. Different techniques such as the Rural Chinese Postman Tour and compaction by test overlapping, are fully analyzed for achieving the desired figures of merit.Novel analytical frameworks such as the fault model and the test sequence generation, are proposed to facilitate a better understanding of the conformance testing process for the practicing engineer as well as an academic audience.
Complex computer-integrated systems offer enormous benefits across a wide array of applications, including automated production, transportation, concurrent software, and computer operating systems, computer networks, distributed database systems, and many other automated systems. Yet, as these systems become more complex, automated, distributed, and computing-intensive, the opportunity for deadlock issues rises exponentially. Deadlock modeling, detection, avoidance, and recovery are critical to improving system performance. Deadlock Resolution in Computer-Integrated Systems is the first text to summarize and comprehensively treat this issue in a systematic manner. Consisting of contributions from prominent researchers in the field, this book addresses deadlock-free models and scheduling, detection and recovery methods, the formulation of dynamic control policies, and comparison and industrial benchmark studies that evaluate various approaches. The editors lay the foundation for exploring deadlock issues with a typical example of an automated manufacturing process, illustrating three primary modeling methods (digraphs, Petri nets, and automata) and comparing their respective advantages and disadvantages. Providing all of the important models and resolution approaches, this book is the complete guide for electrical and control engineers and manufacturing, intelligent, and network systems designers to prevent and manage deadlock issues in their systems.
This volume introduces important modeling and formal techniques for verifying the reliability and correctness of high-assurance software systems, with a focus on the efficient analysis of large-scale systems based on the concept of compositional verification of modules. Juan (Chung Yuan Christian U.) and Tsai (U. of Illinois at Chicago) present seven chapters that discuss introductory material, verification techniques for concurrent systems, multiset labeled transition systems, compositional verification using MLTS and Petri nets, tools and experiments, and delay time Petri nets and net reduction. Application areas include concurrent, distributed, embedded, and real- time systems. Annotation copyrighted by Book News, Inc., Portland, OR.
The refereed proceedings of the 8th International Conference on Reliable Software Technologies, Ada-Europe 2003, held in Toulouse, France in June 2003. The 29 revised full papers presented together with 3 invited papers were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on Ravenscar, language issues, static analysis, distributed information systems, software metrics, software components, formal specification, real-time kernel, software testing, and real-time systems design.
Proceedings of the 7th International Workshop on Software Specification and Design held in Redondo Beach, California, in December 1993. Among the topics discussed: real-time systems, concurrency and distribution, formal reasoning, and design methods and software architecture. No index. Annotation co