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The first and only book to explain the architecture, function, and application of the Intel i386SL microprocessor. Both engineers and programmers will discover comprehensive coverage of system internals and programming techniques with an eye towards implementing this advanced microprocessor.
80486 System Architecture describes the hardware architecture of PC products using the Intel family of 80486 chips, providing a clear, concise explanation of the 80486 processor's relationship to the rest of the system. The author provides a comprehensive treatment of the processor including: -80486 microarchitecture and its functional units -internal and external caches -hardware interface -SL technology features -instructions new to the 80486 -the register set -486/487SX processors -486DX2 processors -486DX2 write-back enhanced processor -486DX4 processors -implementation-specific issues -main memory subsystem design -OverDrive processors If you design or test hardware or software that involves 486 processors, 80486 System Architecture is an essential, time-saving tool. The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer's perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification. The PC System Architecture Series features step-by-step descriptions and instructions and accessible illustrations that enable a wide range of readers to easily understand difficult hardware topics. The authors, expert hardware training consultants for clients including IBM, Intel, Compaq, and Dell, have mastered the art of pinpointing and succinctly explaining just the critical information that PC programmers, software and hardware designers, and engineers need to know and leaving out the rest. The result is an exciting series of books that will enable readers of a wide range of backgrounds to make immediate gains in programming productivity.
Decreasing power dissipation per logic function has become a primary concern in virtually all CMOS system chips designed today as a result of the relentless progress in processing technology that has led us into the deep-submicron age. Evolution from 1 micron to 0.1 micron lithography in the next decade will not be possible without a change in the way we design CMOS systems. But power reduction requires an overall optimisation, ranging from software compilation over instruction set design down to the introduction of much more parallelism in the architecture, the optimal use of memory hierarchy, new clocking strategies, use of asynchronous techniques, new CMOS circuit techniques and management of leakage currents in new low power technologies. Moreover, performance and power dissipation will come to be dominated by interconnect and thus completely new floor planning and place and route strategies are emerging. The chapters in this book present a systematic coverage of deep submicron CMOS digital system design for low power, from process technology all the way up to software design and embedded software systems. Audience: An excellent guide for the practising engineer, researcher and student interested in this crucial aspect of actual CMOS design.
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Written by the world’s most prominent microprocessor design leaders from industry and academia, this book provides complete coverage of all aspects of complex microprocessor design: technology, power management, clocking, high-performance architecture, design methodologies, memory and I/O design, computer aided design, testing and design for testability. The chapters provide state-of-the-art knowledge while including sufficient tutorial material to bring non-experts up to speed. A useful companion to design engineers working in related areas.
A survey of architectural mechanisms and implementation techniques for exploiting fine- and coarse-grained parallelism within microprocessors. Beginning with a review of past techniques, the monograph provides a comprehensive account of state-of-the-art techniques used in microprocessors, covering both the concepts involved and implementations in sample processors. The whole is rounded off with a thorough review of the research techniques that will lead to future microprocessors. XXXXXXX Neuer Text This monograph surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. It presents a comprehensive account of state-of-the-art techniques used in microprocessors that covers both the concepts involved and possible implementations. The authors also provide application-oriented methods and a thorough review of the research techniques that will lead to the development of future processors.