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Si complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuously scaling of its feature size. As scaling is approaching its physical limitations, new materials and device structures are expected. High electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k/metal metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability. A comprehensive study on III-V MOSFETs has been presented here focusing on three areas: 1) III-V/high-k/metal gate stack: material and electrical properties of various high-k dielectrics on III-V substrates have been systematically examined; 2) device architecture: device structures from planar surface channel MOSFETs and buried channel quantum well FETs (QWFETs) to 3D gate-wrapped-around FETs (GWAFETs) and tunneling FETs (TFETs) have been designed and analyzed; 3) fabrication process: process flow has been set up and optimized to build scaled planar and 3D devices with feature size down to 40nm. Potential of high performances have been demonstrated using novel III-V/high-k devices. Effective channel mobility was significantly improved by applying buried channel QWFET structure. Short channel effect control for sub-100nm devices was enhanced by shrinking gate dielectrics, reducing channel thickness and moving from 2D planar to 3D GWAFET structure. InGaAs TFETs have also been developed for ultra-low power application. This research work demonstrates that III-V/high-k/metal MOSFETs with superior device performances are promising candidates for future ultimately scaled logic devices.
Fundamentals of III-V Semiconductor MOSFETs presents the fundamentals and current status of research of compound semiconductor metal-oxide-semiconductor field-effect transistors (MOSFETs) that are envisioned as a future replacement of silicon in digital circuits. The material covered begins with a review of specific properties of III-V semiconductors and available technologies making them attractive to MOSFET technology, such as band-engineered heterostructures, effect of strain, nanoscale control during epitaxial growth. Due to the lack of thermodynamically stable native oxides on III-V's (such as SiO2 on Si), high-k oxides are the natural choice of dielectrics for III-V MOSFETs. The key challenge of the III-V MOSFET technology is a high-quality, thermodynamically stable gate dielectric that passivates the interface states, similar to SiO2 on Si. Several chapters give a detailed description of materials science and electronic behavior of various dielectrics and related interfaces, as well as physics of fabricated devices and MOSFET fabrication technologies. Topics also include recent progress and understanding of various materials systems; specific issues for electrical measurement of gate stacks and FETs with low and wide bandgap channels and high interface trap density; possible paths of integration of different semiconductor materials on Si platform.
Currently, the term 3D integration includes a wide variety of different integration methods, such as 2.5-dimensional (2.5D) interposer-based integration, 3D integrated circuits (3D ICs), 3D systems-in-package (SiP), 3D heterogeneous integration, and monolithic 3D ICs. The goal of this book is to provide readers with an understanding of the latest challenges and issues in 3D integration. TSVs are not the only technology element needed for 3D integration. There are numerous other key enabling technologies required for 3D integration, and the speed of the development in this emerging field is very rapid. To provide readers with state-of-the-art information on 3D integration research and technology developments, each chapter has been contributed by some of the world’s leading scientists and experts from academia, research institutes, and industry from around the globe. Covers chip/wafer level 3D integration technology, memory stacking, reconfigurable 3D, and monolithic 3D IC. Discusses the use of silicon interposer and organic interposer. Presents architecture, design, and technology implementations for 3D FPGA integration. Describes oxide bonding, Cu/SiO2 hybrid bonding, adhesive bonding, and solder bonding. Addresses the issue of thermal dissipation in 3D integration.
This book contains reviews of recent experimental and theoretical results related to nanomaterials. It focuses on novel functional materials and nanostructures in combination with silicon on insulator (SOI) devices, as well as on the physics of new devices and sensors, nanostructured materials and nano scaled device characterization. Special attention is paid to fabrication and properties of modern low-power, high-performance, miniaturized, portable sensors in a wide range of applications such as telecommunications, radiation control, biomedical instrumentation and chemical analysis. In this book, new approaches exploiting nanotechnologies (such as UTBB FD SOI, Fin FETs, nanowires, graphene or carbon nanotubes on dielectric) to pave a way between “More Moore” and “More than Moore” are considered, in order to create different kinds of sensors and devices which will consume less electrical power, be more portable and totally compatible with modern microelectronics products.
This book discusses modern-day Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and future trends of transistor devices. This book provides an overview of Field Effect Transistors (FETs) by discussing the basic principles of FETs and exploring the latest technological developments in the field. It covers and connects a wide spectrum of topics related to semiconductor device physics, physics of transistors, and advanced transistor concepts. This book contains six chapters. Chapter 1 discusses electronic materials and charge. Chapter 2 examines junctions, discusses contacts under thermal-equilibrium, metal-semiconductor contacts, and metal-insulator-semiconductor systems. Chapter 3 covers traditional planar Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Chapter 4 describes scaling-driving technological variations and novel dimensions of MOSFETs. Chapter 5 analyzes Heterojunction Field Effect Transistors (FETs) and also discusses the challenges and rewards of heteroepitaxy. Finally, Chapter 6 examines FETs at molecular scales. Links the discussion of contemporary transistor devices to physical processes Material has been class-tested in undergraduate and graduate courses on the design of integrated circuit components taught by the author Contains examples and end-of-chapter problems Field Effect Transistors, A Comprehensive Overview: From Basic Concepts to Novel Technologies is a reference for senior undergraduate / graduate students and professional engineers needing insight into physics of operation of modern FETs. Pouya Valizadeh is Associate Professor in the Department of Electrical and Computer Engineering at Concordia University in Quebec, Canada. He received B.S. and M.S. degrees with honors from the University of Tehran and Ph.D. degree from The University of Michigan (Ann Arbor) all in Electrical Engineering in 1997, 1999, and 2005, respectively. Over the past decade, Dr. Valizadeh has taught numerous sections of five different courses covering topics such as semiconductor process technology, semiconductor materials and their properties, advanced solid state devices, transistor design for modern CMOS technology, and high speed transistors.
III-V compound semiconductors are of interest as channel materials for next-generation metal-oxide-semiconductor field effect transistors (MOSFETs), as silicon devices reach their fundamental materials limitations. The high electron mobilities of III-V semiconductors potentially allow for higher saturation velocities and further performance scaling. High dielectric constant (k) gate oxides are essential for MOSFET devices and are a major challenge in developing III-V MOSFETs. Interfaces between dielectrics and III-V semiconductors exhibit extremely large interface trap densities, which degrade the transistor performance. Quantitative methods are required to estimate the interface electrical properties and to optimize the interfaces. Methods developed for Si interfaces cannot directly be applied because of differences in the band structures.
Strain Effect in Semiconductors: Theory and Device Applications presents the fundamentals and applications of strain in semiconductors and semiconductor devices that is relevant for strain-enhanced advanced CMOS technology and strain-based piezoresistive MEMS transducers. Discusses relevant applications of strain while also focusing on the fundamental physics pertaining to bulk, planar, and scaled nano-devices. Hence, this book is relevant for current strained Si logic technology as well as for understanding the physics and scaling for future strained nano-scale devices.
This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.
Suitable gate dielectrics are needed for III-V channel metal-oxide-semiconductor field-effect transistors (MOSFETs). III-V semiconductor surfaces tend to have high interface trap state density (Dit). High quality gate dielectrics require a high dielectric constant, a stable interface, and low Dit. The major challenges are scaling down the dielectric to achieve high capacitance densities, understanding defects at the oxide/semiconductor interface, and developing techniques to passivate Dit at the interface. By using nitrogen plasma pre-treatment passivation technique, MOSCAPs with ALD HfO2 directly on InGaAs as high-k gate stack, with accumulation capacitance density 2.4 F/cm2 (EOT=0.6 nm) and 2.5 x 1012 cm2 eV-1 midgap Dit have been achieved.