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"The book comprehensively covers all the current and the emerging areas of the physics and the technology of high permittivity gate dielectric materials, including, topics such as MOSFET basics and characteristics, hafnium-based gate dielectric materials, Hf-based gate dielectric processing, metal gate electrodes, flat-band and threshold voltage tuning, channel mobility, high-k gate stack degradation and reliability, lanthanide-based high-k gate stack materials, ternary hafnia and lanthania based high-k gate stack films, crystalline high-k oxides, high mobility substrates, and parameter extraction. Each chapter begins with the basics necessary for understanding the topic, followed by a comprehensive review of the literature, and ultimately graduating to the current status of the technology and our scientific understanding and the future prospects." .
In this work, the reliability of HfO2 (hafnium oxide) with poly gate and dual metal gate electrode (Ru–Ta alloy, Ru) was investigated. Hard breakdown and soft breakdown, particularly the Weibull slopes, were studied under constant voltage stress. Dynamic stressing has also been used. It was found that the combination of trapping and detrapping contributed to the enhancement of the projected lifetime. The results from the polarity dependence studies showed that the substrate injection exhibited a shorter projected lifetime and worse soft breakdown behavior, compared to the gate injection. The origin of soft breakdown (first breakdown) was studied and the results suggested that the soft breakdown may be due to one layer breakdown in the bilayer structure (HfO2/SiO2: 4 nm/4 nm). Low Weibull slope was in part attributed to the lower barrier height of HfO2 at the interface layer. Interface layer optimization was conducted in terms of mobility, swing, and short channel effect using deep submicron MOSFET devices.
The main goal of this book is to review at the nano and atomic scale the very complex scientific issues that pertain to the use of advanced high dielectric constant (high-k) materials in next generation semiconductor devices. One of the key obstacles to integrate this novel class of materials into Si nano-technology are the electronic defects in high-k dielectrics. It has been established that defects do exist in high-k dielectrics and they play an important role in device operation. The unique feature of this book is a special focus on the important issue of defects. The subject is covered from various angles, including silicon technology, processing aspects, materials properties, electrical defects, microstructural studies, and theory. The authors who have contributed to the book represents a diverse group of leading scientists from academic, industrial and governmental labs worldwide who bring a broad array of backgrounds (basic and applied physics, chemistry, electrical engineering, surface science, and materials science). The contributions to this book are accessible to both expert scientists and engineers who need to keep up with leading edge research, and newcomers to the field who wish to learn more about the exciting basic and applied research issues relevant to next generation device technology.
For next generation MOSFETs, the constant field scaling rule dictates a reduction in the gate oxide thickness among other parameters. Consequently, gate leakage current becomes a serious issue with very thin SiO2 that is conventionally used as gate dielectric since it is the native oxide for Si substrate. This has driven an industry wide search for suitable alternate 'high-k' gate dielectric that has a high value of relative permittivity compared to SiO2 thereby presenting a physically thicker barrier for tunneling carriers while providing a high gate capacitance. Consequently, it is essential to study the properties of these novel materials and the interfaces that they form with the substrate, gate or other dielectrics in a multi-level stack. The main focus of this work is the 1/f noise that is specifically used as a characterization tool to evaluate the performance of high-k MOSFETs. Nevertheless, DC and split C-V characterization are done as well to obtain device performance parameters that are used in the noise analysis. At first, the room temperature 1/f noise characteristics are presented for n- and p-channel poly-Si gated MOSFETs with three different gate dielectrics- HfO2, Al2O3 (top layer)/HfO2 (bottom layer), HfAlOx. The devices had either 1 nm or 4 nm SiO2 interfacial layer, thus presenting an opportunity to understand the effects of interfacial layer thickness on noise and carrier mobility. In the initial study, the analysis of noise is done based on the Unified Flicker Noise Model. Next, a comparative study of 1/f noise behavior is presented for TaSiN (NMOS) and TiN (PMOS) gated MOSFETs with HfO2 gate dielectric and their poly-Si gated counterparts. Additionally, in TaSiN MOSFETs, the effect of the different deposition methods employed for interfacial layer formation on the overall device performance is studied. Finally, the 'Multi-Stack Unified Noise' model (MSUN) is proposed to better model/characterize the 1/f noise in multi-layered high-k MOSFETs. This model takes the non-uniform trap density profile and other physical properties of the constituent gate dielectrics into account. The MSUN model is shown to be in excellent agreement with the experimental data obtained on TaSiN/HfO 2/SiO2 MOSFETs in the 78-350 K range. Additionally, the MSUN model is expressed in terms of surface potential based parameters for inclusion in to the circuit simulators.
Comprehensive reference on the fundamental principles and basic physics dictating metal–oxide–semiconductor field-effect transistor (MOSFET) operation Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal–oxide–semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs. Additional topics covered include: High-k gate dielectrics and metal gate electrodes for multi-gate MOSFETs, covering gate stack processing and metal gate modification Strain engineering in 3D complementary metal-oxide semiconductors (CMOS) and its scaling impact, and strain engineering in silicon–germanium (SiGe) FinFET and its challenges and future perspectives TCAD simulation of multi-gate MOSFET, covering model calibration and device performance for analog and RF applications Description of the design of an analog amplifier circuit using digital CMOS technology of SCL for ultra-low power VLSI applications Advanced Nanoscale MOSFET Architectures helps readers understand device physics and design of new structures and material compositions, making it an important resource for the researchers and professionals who are carrying out research in the field, along with students in related programs of study.
Issues relating to the high-K gate dielectric are among the greatest challenges for the evolving International Technology Roadmap for Semiconductors (ITRS). More than just an historical overview, this book will assess previous and present approaches related to scaling the gate dielectric and their impact, along with the creative directions and forthcoming challenges that will define the future of gate dielectric scaling technology.