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In today’s world everything is going toward speed and comfort. This includes differenttechnologies which their improvement leads to an easier life for human beings. One of thesetechnologies is nanotechnology that deals with fabrication and structures of objects in nanometerscale.Today’s technology and science has proved that nanowires are excellent candidates forfabrication of many different devices and their components. These devices take less space whilehaving high performance. Nanowires are one-dimensional structures that have many applicationsincluding a variety of sensors, transistors as well as energy-storage devices like solar cells andLi-ion batteries.Fabrication of nanowires is still under research and many universities and institutes are trying tofind methods that are both time- and cost-efficient. This is a challenging subject since there aremany parameters involved in the process and each of these parameters affect the final results offabrication.The concentration of this work is on fabrication of silicon nanowires. Silicon is the second-mostabundant element on the earth and therefore has a more reasonable price compare to otherelements.There are many different techniques to fabricate silicon nanowires but most of these methods areexpensive and time consuming.In this work we have used a top-down method which is time and cost efficient compare to otherfabrication methods. There are three main steps in our work; anisotropic etching to texture thesurface of the silicon wafer, electrochemical etching to produce the nanowires and a post-etchingprocess in order to clean the surface of the sample. Wafer type, etching duration, temperature,and the applied current are the parameters that are studied during the experiments. The fabricatednanowires are captured and characterized using scanning electron microscopy.
Nanoscale materials are showing great promise in various electronic, optoelectronic, and energy applications. Silicon (Si) has especially captured great attention as the leading material for microelectronic and nanoscale device applications. Recently, various silicides have garnered special attention for their pivotal role in Si device engineering
When dimensions of material approach nanoscale, they often reveal startling properties. These unique properties when compared to bulk material make them interesting candidates for new technologies. In a race to sustain Moore's Law, silicon nanowires which possess remarkable properties diverse from bulk-silicon have gained notable attention. With advancement in technology engineers have mastered the art of fabrication of nanowires, but there exists a big gap in understanding various phenomena at this scale. The aim of this work is to bridge the gap and give an insight into some interesting properties and application of silicon nanowires. Using top-down lithography Silicon nanowires are fabricated and various mechanical and electrical properties are studied. The use of functionalized silicon nanowires for gas detection is demonstrated with very large sensitivity and detection window reported for the first time.
Thermoelectric devices, which convert temperature gradients into electricity, have the potential to harness waste heat to improve overall energy efficiency. However, current thermoelectric devices are not cost-effective for most applications due to their low efficiencies and high material costs. To improve the overall conversion efficiency, thermoelectric materials should possess material properties that closely resemble a "phonon glass" and an "electron crystal". The desired low thermal and high electrical conductivities allow the thermoelectric device to maintain a high temperature gradient while effectively transporting current. Unfortunately, thermal transport and electrical transport are a closely coupled phenomena and it is difficult to independently engineer each specific conduction mechanism in conventional materials. One strategy to realize this is to generate nanostructured silicon (e.g. silicon nanowires (SiNWs)), which have been shown to reduce thermal conductivity ([kappa]) through enhanced phonon scattering while theoretically preserving the electronic properties; therefore, improving the overall device efficiency. The ability to suppress phonon propagation in nanostructured silicon, which has a bulk phonon mean free path ~ 300 nm at 300 K, has raised substantial interest as an ultra-low [kappa] material capable of reducing the thermal conductivity up to three orders of magnitude lower than that of bulk silicon. While the formation of porous silicon and SiNWs has individually been demonstrated as promising methods to reduce [kappa], there is a lack of research investigating the thermal conductivity in SiNWs containing porosity. We fabricated SiNW arrays using top-down etching methods (deep reactive ion etching and metal-assisted chemical etching) and by tuning the diameter with different patterning methods and tuning the internal porosity with different SiNW etching conditions. The effects of both the porosity and the SiNW dimensions at the array scale are investigated by measuring [kappa] of vertical SiNW arrays using a nanosecond time-domain thermoreflectance technique. In addition to thermoelectric devices, vertical SiNW arrays, due to their anisotropic electronic and optical properties, large surface to volume ratios, resistance to Li-ion pulverization, ability to orthogonalize light absorption and carrier transport directions, and trap light, make vertical SiNW arrays important building blocks for various applications. These may include sensors, solar cells, and Li-ion batteries. Many of these applications benefit from vertical SiNW arrays fabricated on non-silicon based substrates which endow the final devices with the properties of flexibility, transparency, and light-weight while removing any performance limitation of the silicon fabrication substrate. We then developed two vertical transfer printing methods (V-TPMs) that are used to detach SiNW arrays from their original fabrication substrates and subsequently attach them to any desired substrate while retaining their vertical alignment over a large area. The transfer of vertically aligned arrays of uniform length SiNWs is desirable to remove the electrical, thermal, optical, and structural impact from the fabrication substrate and also to enable the integration of vertical SiNWs directly into flexible and conductive substrates. Moreover, realization of a thermoelectric device requires the formation of electrical contacts on both sides of the SiNW arrays. We formed metallic contacts on both ends of the SiNW arrays with a mechanical supporting and electrical insulating polymer in between. Electrical characterization of the SiNW devices exhibited good current-voltage (I-V) characteristics independent of substrates materials and bending conditions. We believe the V-TPMs developed in this work have great potential for manufacturing practical thermoelectric devices as well as high performing, scalable SiNW array devices on flexible and conducting substrates.
Covering technological aspects as well as the suitability and applicability of various kinds of uses, this handbook shows optimization strategies, techniques and assembly pathways to achieve the combination of complex, even three-dimensional structures with simple manufacturing steps. The authors provide information on markets, commercialization opportunities and aspects of mass or large-scale production as well as design tools, experimental techniques, novel materials, and ideas for future improvements. Not only do they weigh up cost versus quantity, they also consider CMOS and LIGA strategies. Of interest to physicists, electronics engineers, materials scientists, institutional and industrial libraries as well as graduate students of the relevant disciplines.
Controlled and ordered growth of Si nanowires through a low temperature fabrication method compatible with CMOS processing lines is a highly desirable replacement to future electronic fabrication technologies as well as a candidate for a low cost route to inexpensive photovoltaics. This stems from the fact that traditional CMOS based electronics are hitting physical barriers that are slowing the Moore's Law trend as well as the demand for an inexpensive solar cell technology that can obtain grid parity. A fractional factorial growth study is presented that compares the growth of Au and Al catalyzed Si nanowires at temperatures ranging from 150 to 400° C. Dense and prolific growth of Si nanowires on 111 and 100 Si substrates as well as glass substrates was obtained using a Au catalyst at temperatures of 400° C. An overview is given that considers all growth experiments and includes TEM analysis of individual Si nanowires grown on Si substrates showing nanowires to be both crystalline and amorphous in nature. Optical transmission data of bulk Si nanowire films on glass substrates showed that the collective optical properties were highly desirable as transmission was minimized over the 300 to 1400 nm wavelength range at different transmission angles. Collectively, a growth platform is presented from which further material study will yield advanced Si nanowire based devices, satisfying a demand by the ITRS and the scientific community at large for electronics that can continue the Moore's law trend and inexpensive photovoltaics capable of meeting the consumer demand for grid parity.
Over the last several decades, the demand for real-time data processing and storage has exponentially increased and pushed the semiconductor field to its fabrication limits. Traditional methods of semiconductor nanomanufacturing, like lithography and reactive ion etching (RIE), suffer from feature resolution and etch taper limits for devices comprising sub-10 nm nanofabrication nodes. Methods like the ones mentioned above are both expensive and difficult to manufacture to keep up with continued scaling requirements of semiconductor fabrication. This thesis presents a fabrication method and metrology characterization of silicon nanowire arrays using a Metal Assisted Chemical Etching (MACE) approach. MACE is a simple, low-cost fabrication technique that allows for high aspect ratio silicon nanostructures to be successfully fabricated without sacrificing geometry fidelity, making it a promising etching method for large-scale semiconductor manufacturing. In this research, small-scale MACE was demonstrated on silicon coupons with an initial process window of 0 nm - 100 nm oxide thickness. Then, a down-selected process window of 10 nm - 50 nm oxide thickness was successfully reproduced on a full-wafer scale (100 mm diameter silicon wafers) at different etchant solution concentrations. The oxide layer serves as a sacrificial layer between the silicon and resist to allow a consistent etching starting point, thus improving the etch depth uniformity and aspect ratios of silicon nanowires. The silicon nanowires were characterized using local scanning electron microscopy (SEM) images by mapping the areas of the wafer as North, South, East, and West to measure critical dimensions such as height and diameter, as well as to observe phenomena such as nanowire collapse