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The goal of this research was to explore and understand the mechanisms involved in the fabrication of silicon nanostructures using metal-assisted etching. We developed a method utilizing metal-assisted etching in conjunction with block copolymer lithography to create ordered and densely-packed arrays of high-aspect-ratio single-crystal silicon nanowires with uniform crystallographic orientations. Nanowires with sub-20 nm diameters were created as either continuous carpets or as carpets within trenches. Wires with aspect ratios up to 220 with much reduced capillary-induced clustering were achieved through post-etching critical point drying. The size distribution of the diameters was narrow and closely followed the size distribution of the block copolymer. Fabrication of wires in topographic features demonstrated the ability to accurately control wire placement. The flexibility of this method will facilitate the use of such wire arrays in micro- and nano-systems in which high device densities and/or high surface areas are desired. In addition, we report a systematic study of metal-catalyzed etching of (100), (110), and (111) silicon substrates using gold catalysts with varying geometrical characteristics. It is shown that for isolated catalyst nanoparticles and metal meshes with small hole spacings, etching proceeded preferentially in the 100 direction. However, etching was confined in the direction vertical to the substrate surface when a catalyst mesh with large hole spacings was used. This result was used to demonstrate the use of metal-assisted etching to create arrays of vertically-aligned polycrystalline and amorphous silicon nanowires etched from deposited silicon thin films using catalyst meshes with relatively large hole spacings. The ability to pattern wires from polycrystalline and amorphous silicon thin films opens the possibility of making silicon nanowire-array-based devices on a much wider range of substrates. Finally, we demonstrated the fabrication of a silicon-nanopillar-based nanocapacitor array using metal-assisted etching and electrodeposition. The capacitance density was increased significantly as a result of an increased electrode area made possible by the catalytic etching approach. We also showed that the measured capacitance densities closely follow the expected trend as a function of pillar height and array period. The capacitance densities can be further enhanced by increasing the array density and wire length with the incorporation of known self-assembly-based patterning techniques such as block copolymer lithography.
Metal-assisted chemical etching (MacEtch) has recently emerged as a new etching technique capable of fabricating high aspect ratio nano- and microstructures in a few semiconductors substrates—Si, Ge, poly-Si, GaAs, and SiC—and using different catalysts—Ag, Au, Pt, Pd, Cu, Ni, and Rh. Several shapes have been demonstrated with a high anisotropy and feature size in the nanoscale—nanoporous films, nanowires, 3D objects, and trenches, which are useful components of photonic devices, microfluidic devices, bio-medical devices, batteries, Vias, MEMS, X-ray optics, etc. With no limitations of large-areas and low-cost processing, MacEtch can open up new opportunities for several applications where high precision nano- and microfabrication is required. This can make semiconductor manufacturing more accessible to researchers in various fields, and accelerate innovation in electronics, bio-medical engineering, energy, and photonics. Accordingly, this Special Issue seeks to showcase research papers, short communications, and review articles that focus on novel methodological developments in MacEtch, and its use for various applications.
Over the last several decades, the demand for real-time data processing and storage has exponentially increased and pushed the semiconductor field to its fabrication limits. Traditional methods of semiconductor nanomanufacturing, like lithography and reactive ion etching (RIE), suffer from feature resolution and etch taper limits for devices comprising sub-10 nm nanofabrication nodes. Methods like the ones mentioned above are both expensive and difficult to manufacture to keep up with continued scaling requirements of semiconductor fabrication. This thesis presents a fabrication method and metrology characterization of silicon nanowire arrays using a Metal Assisted Chemical Etching (MACE) approach. MACE is a simple, low-cost fabrication technique that allows for high aspect ratio silicon nanostructures to be successfully fabricated without sacrificing geometry fidelity, making it a promising etching method for large-scale semiconductor manufacturing. In this research, small-scale MACE was demonstrated on silicon coupons with an initial process window of 0 nm - 100 nm oxide thickness. Then, a down-selected process window of 10 nm - 50 nm oxide thickness was successfully reproduced on a full-wafer scale (100 mm diameter silicon wafers) at different etchant solution concentrations. The oxide layer serves as a sacrificial layer between the silicon and resist to allow a consistent etching starting point, thus improving the etch depth uniformity and aspect ratios of silicon nanowires. The silicon nanowires were characterized using local scanning electron microscopy (SEM) images by mapping the areas of the wafer as North, South, East, and West to measure critical dimensions such as height and diameter, as well as to observe phenomena such as nanowire collapse
Silicon nanowires can enable important applications in energy and healthcare such as biochemical sensors, thermoelectric devices, and ultra-capacitors. In the energy sector, for example, as the need for more efficient energy storage continues to grow for enabling applications such as electric vehicles, high energy storage density capacitors are being explored as a potential replacement to traditional batteries that lack fast charge/discharge rates as well as have shorter life cycles. Silicon nanowire based ultra-capacitors offer increased energy storage density by increasing the surface area per unit projected area of the electrode, thereby allowing more surface “charge” to reside. The motivation behind this dissertation is the study of low-cost techniques for fabrication of high aspect ratio silicon nanowires with controlled geometry with an exemplar application in ultra-capacitors. Controlled transfer of high aspect ratio, nano-scale features into functional device layers requires anisotropic etch techniques. Dry reactive ion etch techniques are commonly used since most solution-based wet etch processes lack anisotropic pattern transfer capability. However, in silicon, anisotropic wet etch processes are available for the fabrication of nano-scale features, but have some constraints in the range of geometry of patterns that they can address. While this lack of geometric and material versatility precludes the use of these processes in applications like integrated circuits, they can be potentially realized for fabricating nanoscale pillars. This dissertation explores the geometric limitations of such inexpensive wet anisotropic etching processes and develops additional methods and geometries for fabrication of controlled nano-scale, high aspect ratio features. Jet and Flash Imprint Lithography (J-FILTM) has been used as the preferred pre-etch patterning process as it enables patterning of sub-50 nm high density features with versatile geometries over large areas. Exemplary anisotropic wet etch processes studied include Crystalline Orientation Dependent Etch (CODE) using potassium hydroxide (KOH) etching of silicon and Metal Assisted Chemical Etching (MACE) using gold as a catalyst to etch silicon. Experiments with CODE indicate that the geometric limitations of the etch process prevent the fabrication of high aspect ratio nanowires without adding a prohibitive number of steps to protect the pillar geometry. On the other hand, MACE offers a relatively simple process for fabricating high aspect ratio pillars with unique cross sections, and has thus been pursued to fabricate fully functional electrostatic capacitors featuring both circular and diamond-shaped nano-pillar electrodes. The capacitance of the diamond-shaped nano-pillar capacitor has been shown to be ~77.9% larger than that of the circular cross section due to the increase in surface area per unit projected area. This increase in capacitance approximately matches the increase calculated using analytical models. Thus, this dissertation provides a framework for the ability to create unique sharp cornered nanowires that can be explored further for a wider variety of cross sections.
Patterning and etching high aspect ratio, sub-50 nanometer structures for 3D device architectures is becoming a critical challenge in advanced semiconductor device fabrication. Metal assisted chemical etching (MACE) is a wet etch process that has demonstrated very high aspect ratio structures in single crystal silicon at sub-50 nanometer scale. The capabilities of this process can be applied to etching of gate structures made in bulk or epitaxially grown single crystal silicon, however, it is important to extend MACE to other materials for a range of semiconductor device architectures. In this research, we build on preliminary results published in the literature showing MACE for polycrystalline silicon. If it can be demonstrated that MACE of polysilicon can retain the sub-50 nanometer resolution and high aspect ratio produced with MACE of single crystal silicon, process techniques can be developed around polysilicon MACE to fabricate critical structures needed in advanced Dynamic RAM, 3D Flash and vias for logic devices. It is also important to demonstrate that atomically precise side walls that are near-perfect in maintaining 90-degree wall angle, as demonstrated with MACE applied to single crystal silicon, can also be achieved in polycrystalline silicon. Metal assisted chemical etching (MACE) is a promising approach that addresses many issues that arise from underperforming reactive ion etching (RIE) methods that have limitations in fabricating high aspect ratio sub-50 nanometer nanostructures due to presence of tapered profiles and high side wall roughness. However, MACE is extremely limited in the types of materials for which it has been demonstrated. MACE has shown reliable etching only in single crystal silicon which limits its applications to a small number of front-end semiconductor device layers. This work extends the capabilities of MACE to polysilicon which when combined with additional process steps has the potential to create patterns for metal vias and deep trench capacitors, both of which are important in the semiconductor industry. Much of the existing literature on MACE for polysilicon builds an underlying hypothesis; etch quality of polysilicon is compromised by the inherent crystalline structure of the material. There is an especial lack in understanding how MACE works at crystal grain boundaries, which presents risk in reduced atomic precision due to sidewall roughness induced by these boundaries –limiting the value of MACE for sub-50 nanometer structures. In this work, we present a MACE wet etch of polysilicon that produces structure arrays with sub-50nm resolution and anisotropic profile. The three demonstrated structures are pillars of 6:1 aspect ratio and 50nm spacing for comparison to MACE literature, pillars of 30nm spacing to establish resolution limitations of polysilicon etch, and a diamond pillar array with potential to fabricate holes with as low as 15nm spacing
Metal-assisted chemical etching (MacEtch) has recently emerged as a new etching technique capable of fabricating high aspect ratio nano- and microstructures in a few semiconductors substrates--Si, Ge, poly-Si, GaAs, and SiC--and using different catalysts--Ag, Au, Pt, Pd, Cu, Ni, and Rh. Several shapes have been demonstrated with a high anisotropy and feature size in the nanoscale--nanoporous films, nanowires, 3D objects, and trenches, which are useful components of photonic devices, microfluidic devices, bio-medical devices, batteries, Vias, MEMS, X-ray optics, etc. With no limitations of large-areas and low-cost processing, MacEtch can open up new opportunities for several applications where high precision nano- and microfabrication is required. This can make semiconductor manufacturing more accessible to researchers in various fields, and accelerate innovation in electronics, bio-medical engineering, energy, and photonics. Accordingly, this Special Issue seeks to showcase research papers, short communications, and review articles that focus on novel methodological developments in MacEtch, and its use for various applications.
The Handbook of Porous Silicon brings together the expertise of a large, international team of almost 100 academic researchers, engineers, and product developers from industry across electronics, medicine, nutrition and consumer care to summarize the field in its entirity with 150 chapters and 5000 references. The volume presents 5 parts which cover fabrication techniques, material properties, characterization techniques, processing and applications. Much attention was given in the the past to its luminescent properties, but increasingly it is the biodegradability, mechanical, thermal and sensing capabilities that are attracting attention. The volume is divided into focussed data reviews with, wherever possible, quantitative rather than qualitative descriptions of both properties and performance. The book is targeted at undergraduates, postgraduates, and experienced researchers.
Silicon device manufacturing, at both the micro and nanoscales, is largely performed using plasma etching techniques such as Reactive Ion Etching. Deep Reactive Ion Etching (DRIE) can be used to create high-aspect ratio nanostructures in silicon. The DRIE process suffers from low throughput, only one wafer can be processed at a time; high cost, the necessary tools and facilities for implementation are expensive; and surface defects such as sidewall taper and scalloping as a consequence of the cycling process required for high-aspect-ratio manufacturing. A potential solution to these issues consists of implementing wet-etching techniques, which do not require expensive equipment and can be implemented at a batch scale. Metal Assisted Chemical Etch is a wet-etch process that uses a metal catalyst to mediate silicon oxidation and removal in a diffusion-based process. This process has been demonstrated to work for both micro and nanoscale feature manufacturing on silicon substrates. To date, however, a single study aimed at identifying experimental conditions for successful multi-scale (integrated micro- and nanoscale) manufacturing is lacking in the literature. This mixed micro-nanoscale etching process (IMN-MACE) can enable a wide variety of applications including, for example, development of point-of-care medical diagnostic devices which rely on micro- and nano-fluidic sample processing, a growing field in the area of preventive medicine. This work developed multi-scale MACE by a systematic experimental exploration of the process space. A total of 54 experiments were performed to study the effects of the following process parameters: (i) surface silicon dioxide, (ii) metal catalyst stack, (iii) etchant solution concentration, and (iv) pre-etch sample preparation. Of these 54 experiments, 18 experiments were based on exploring nanopatterning of 100nm pillars, and the remaining 36 explored the fabrication of micropillars with a diameter between 10μm and 50μm in 5μm increments. It was determined that a single catalyst stack consisting of ~3nm Ag underneath a ~15nm Au metal layer can be used to etch high quality features at both the micro and nanoscales on a silicon substrate pre-treated with hydrogen fluoride to remove the native oxide layer from the surface. Future steps for micro-nano scale integration were also proposed
Edited by the leaders in the fi eld, with chapters from highly renowned international researchers, this is the fi rst coherent overview of the latest in silicon nanomembrane research. As such, it focuses on the fundamental and applied aspects of silicon nanomembranes, ranging from synthesis and manipulation to manufacturing, device integration and system level applications, including uses in bio-integrated electronics, three-dimensional integrated photonics, solar cells, and transient electronics. The first part describes in detail the fundamental physics and materials science involved, as well as synthetic approaches and assembly and manufacturing strategies, while the second covers the wide range of device applications and system level demonstrators already achieved, with examples taken from electronics and photonics and from biomedicine and energy.
PHOTOVOLTAIC MANUFACTURING This book covers the state-of-the-art and the fundamentals of silicon wafer solar cells manufacturing, written by world-class researchers and experts in the field. High quality and economic photovoltaic manufacturing is central to realizing reliable photovoltaic power supplies at reasonable cost. While photovoltaic silicon wafer manufacturing is at a mature, industrial and mass production stage, knowing and applying the fundamentals in solar manufacturing is essential to anyone working in this field. This is the first book on photovoltaic wet processing for silicon wafers, both mono- and multi-crystalline. The comprehensive book provides information for process, equipment, and device engineers and researchers in the solar manufacturing field. The authors of the chapters are world-class researchers and experts in their field of endeavor. The fundamentals of wet processing chemistry are introduced, covering etching, texturing, cleaning and metrology. New developments, innovative approaches, as well as current challenges are presented. Benefits of reading the book include: The book includes a detailed discussion of the important new development of black silicon, which is considered to have started a new wave in photovoltaics and become the new standard while substantially lowering the cost. Photovoltaics are central to any country’s “New Green Deal” and this book shows how to manufacture competitively. The book’s central goal is to show photovoltaic manufacturing can be done with enhanced quality and lowering costs. Audience Engineers, chemists, physicists, process technologists, in both academia and industry, that work with photovoltaics and their manufacture.