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This Lecture Notes volume is based on the "International Workshop on High Performance Transaction Systems" held in the Asilomar Conference Center, September 28-30, 1987. Many of the problems identified during the workshop are liable to determine the future development of transaction systems and distributed high performance systems in general for many years to come. So the organizers of HPTS '87 felt encouraged to collect the papers presented at the workshop in order to make them accessible to a wider audience of interested developers and researchers. Since some of the contributions represented work in progress, the authors agreed to prepare revised and updated versions of their papers for this publication. This accounts for the long delay between the event itself and the publication, but on the other hand it provides the reader with a state-of-the-art account of transaction processing topics. The book is organized according to the major sections of the workshop. In the network section the reader finds an analysis of two of the major "paradigms" in networking, ISO/OSI and SNA, from the perspective of transaction processing. In the next section four different transaction processing and database systems are described: Model 204 - a database management system marketed by Computer Corporation of America, Tandem's NonStop SQL, Citicorp's transaction processing system and ALCS, which basically is a version of TPF running under MVS/XA. The section on architectural issues contains four very different contributions which are fairly representative of the type of problems in transaction systems investigated in the research community. Finally, performance evaluations and system comparisons are presented.
The State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro cessors. CPU speeds are approximately doubling every eighteen months, while main memory speed doubles about every ten years. The International Tech nology Roadmap for Semiconductors (ITRS) study suggests that memory will remain on its current growth path. The ITRS short-and long-term targets indicate continued scaling improvements at about the current rate by 2016. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years. A similar growth pattern is forecast for other high-density chip areas and high-performance logic (e.g., microprocessors and application specific inte grated circuits (ASICs)). In the future, molecular devices, 64 gigabit DRAMs and 28 GHz clock signals are targeted. Although densities continue to grow, we still do not see significant advances that will improve memory speed. These trends have created a problem that has been labeled the Memory Wall or Memory Gap.
Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This third issue contains 14 papers carefully reviewed and selected out of numerous submissions and is divided into four sections. The first section contains the top four papers from the Third International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, in January 2008. The second section consists of four papers from the 8th MEDEA Workshop held in conjunction with PACT 2007 in Brasov, Romania, in September 2007. The third section contains two regular papers and the fourth section provides a snapshot from the First Workshop on Programmability Issues for Multicore Computers, MULTIPROG, held in conjunction with HiPEAC 2008.
For the technological progress in communication technology it is necessary that the advanced studies in circuit and software design are accompanied with recent results of the technological research and physics in order to exceed its limitations. This book is a guide which treats many components used in mobile communications, and in particular focuses on non-volatile memories. It emerges following the conducting line of the non-volatile memory in the wireless system: On the one hand it develops the foundations of the interdisciplinary issues needed for design analysis and testing of the system. On the other hand it deals with many of the problems appearing when the systems are realized in industrial production. These cover the difficulties from the mobile system to the different types of non-volatile memories. The book explores memory cards, multichip technologies, and algorithms of the software management as well as error handling. It also presents techniques of assurance for the single components and a guide through the Datasheet lectures.
This volume is the first in a series which aims to contribute to the wider dissemination of the results of research and development in database systems for non-traditional applications and non-traditional machine organizations. It contains updated versions of selected papers from the First International Symposium on Database Systems for Advanced Applications.