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Every day, companies call upon their signal integrity engineers to make difficult decisions about design constraints and timing margins. Can I move these wires closer together? How many holes can I drill in this net? How far apart can I place these chips? Each design is unique: there’s no single recipe that answers all the questions. Today’s designs require ever greater precision, but design guides for specific digital interfaces are by nature conservative. Now, for the first time, there’s a complete guide to timing analysis and simulation that will help you manage the tradeoffs between signal integrity, performance, and cost. Writing from the perspective of a practicing SI engineer and team lead, Greg Edlund of IBM presents deep knowledge and quantitative techniques for making better decisions about digital interface design. Edlund shares his insights into how and why digital interfaces fail, revealing how fundamental sources of pathological effects can combine to create fault conditions. You won’t just learn Edlund’s expert techniques for avoiding failures: you’ll learn how to develop the right approach for your own projects and environment. Coverage includes • Systematically ensure that interfaces will operate with positive timing margin over the product’s lifetime–without incurring excess cost • Understand essential chip-to-chip timing concepts in the context of signal integrity • Collect the right information upfront, so you can analyze new designs more effectively • Review the circuits that store information in CMOS state machines–and how they fail • Learn how to time common-clock, source synchronous, and high-speed serial transfers • Thoroughly understand how interconnect electrical characteristics affect timing: propagation delay, impedance profile, crosstalk, resonances, and frequency-dependent loss • Model 3D discontinuities using electromagnetic field solvers • Walk through four case studies: coupled differential vias, land grid array connector, DDR2 memory data transfer, and PCI Express channel • Appendices present a refresher on SPICE modeling and a high-level conceptual framework for electromagnetic field behavior Objective, realistic, and practical, this is the signal integrity resource engineers have been searching for. Preface xiii Acknowledgments xvi About the Author xix About the Cover xx Chapter 1: Engineering Reliable Digital Interfaces 1 Chapter 2: Chip-to-Chip Timing 13 Chapter 3: Inside IO Circuits 39 Chapter 4: Modeling 3D Discontinuities 73 Chapter 5: Practical 3D Examples 101 Chapter 6: DDR2 Case Study 133 Chapter 7: PCI Express Case Study 175 Appendix A: A Short CMOS and SPICE Primer 209 Appendix B: A Stroll Through 3D Fields 219 Endnotes 233 Index 235
Practical Reliability of Electronic Equipment and Products will help electrical, electronics, manufacturing, mechanical, systems design, and reliability engineers; electronics production managers; electronic circuit designers; and upper-level undergraduate and graduate students in these disciplines.
Cogently addressing the future of signal integrity and the effect it will have on the data transmission industry as a whole, this all-inclusive guide addresses a wide array of technologies, from traditional digital data transmission to microwave measurements, and accessibly examines the gap between the two. Focusing on real world applications and providing a wide array of case studies that show how each technology can be used—from backplane design challenges to advanced error correction techniques—this guide addresses many of today’s high-speed technologies while also providing excellent insight into their future direction. With numerous valuable lessons pertaining to the signal integrity industry, this resource is the ultimate must-read guide for any specialist in the design engineering field.
iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.
& Describes the engineering needs addressed by the individual EDA tools and covers EDA from both the provider and user viewpoints. & & Learn the importance of marketing and business trends in the EDA industry. & & The EDA consortium is made up of major corporations including SUN, HP, and Intel.
Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation.
As the complexity of electronic systems continues to increase, the micro-electronic industry depends upon automation and simulations to adapt quickly to market changes and new technologies. Compiled from chapters contributed to CRC's best-selling VLSI Handbook, this volume of the Principles and Applications in Engineering series covers a broad rang
This unique book provides you with practical guidance on understanding and interpreting signal integrity (SI) performance to help you with your challenging circuit board design projects. You find high-level discussions of important SI concepts presented in a clear and easily accessible format, including question and answer sections and bulleted lists. This valuable resource features rules of thumb and simple equations to help you make estimates of critical signal integrity parameters without using circuit simulators of CAD (computer-aided design). The book is supported with over 120 illustrations, nearly 100 equations, and detailed reference lists at the end of each chapter.
"...offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity." —Jake Buurma, Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc. Covers signal integrity effects in high performance Radio Frequency (RF) IC Brings together research papers from the past few years that address the broad range of issues faced by IC designers and CAD managers now and in the future A Wiley-IEEE Press publication