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Machine learning has proliferated on many Internet-of-Things (IoT) applications designed for edge devices. Energy efficiency is one of the most crucial constraints in the design of machine learning applications on IoT devices due to battery and energy-harvesting power sources. Previous attempts use the cloud to transmit data back and forth onto the edge device to alleviate energy strain, but this comes at a great latency and privacy cost. Approximate computing has emerged as a promising solution to bypass the cloud by reducing the energy cost of secure computation ondevice while maintaining high accuracy and low latency. Within machine learning, approximate computing can be used on overparameterized deep neural networks (DNNs) by removing the redundancy by sparsifying the network connections. This thesis attempts to leverage approximate computing techniques on the hardware and software-side of DNNs in order to port onto edge devices with limited power supplies. This thesis aims to implement reconfigurable approximate computing on low-power edge devices, allowing for optimization of the energy-quality tradeoff depending on application specifics. These objectives are achieved by three tasks as follows: i) hardware-side memory-aware logic synthesization, ii) designing energy-aware model compression techniques, and, iii) optimizing edge offloading techniques for efficient client and server communication. These contributions will help facilitate the efficient implementation of edge machine learning on resource-constrained embedded systems.
This book presents recent advances towards the goal of enabling efficient implementation of machine learning models on resource-constrained systems, covering different application domains. The focus is on presenting interesting and new use cases of applying machine learning to innovative application domains, exploring the efficient hardware design of efficient machine learning accelerators, memory optimization techniques, illustrating model compression and neural architecture search techniques for energy-efficient and fast execution on resource-constrained hardware platforms, and understanding hardware-software codesign techniques for achieving even greater energy, reliability, and performance benefits.
EXPLAINABLE MACHINE LEARNING MODELS AND ARCHITECTURES This cutting-edge new volume covers the hardware architecture implementation, the software implementation approach, and the efficient hardware of machine learning applications. Machine learning and deep learning modules are now an integral part of many smart and automated systems where signal processing is performed at different levels. Signal processing in the form of text, images, or video needs large data computational operations at the desired data rate and accuracy. Large data requires more use of integrated circuit (IC) area with embedded bulk memories that further lead to more IC area. Trade-offs between power consumption, delay and IC area are always a concern of designers and researchers. New hardware architectures and accelerators are needed to explore and experiment with efficient machine-learning models. Many real-time applications like the processing of biomedical data in healthcare, smart transportation, satellite image analysis, and IoT-enabled systems have a lot of scope for improvements in terms of accuracy, speed, computational powers, and overall power consumption. This book deals with the efficient machine and deep learning models that support high-speed processors with reconfigurable architectures like graphic processing units (GPUs) and field programmable gate arrays (FPGAs), or any hybrid system. Whether for the veteran engineer or scientist working in the field or laboratory, or the student or academic, this is a must-have for any library.
Deep Learning on Edge Computing Devices: Design Challenges of Algorithm and Architecture focuses on hardware architecture and embedded deep learning, including neural networks. The title helps researchers maximize the performance of Edge-deep learning models for mobile computing and other applications by presenting neural network algorithms and hardware design optimization approaches for Edge-deep learning. Applications are introduced in each section, and a comprehensive example, smart surveillance cameras, is presented at the end of the book, integrating innovation in both algorithm and hardware architecture. Structured into three parts, the book covers core concepts, theories and algorithms and architecture optimization. This book provides a solution for researchers looking to maximize the performance of deep learning models on Edge-computing devices through algorithm-hardware co-design. Focuses on hardware architecture and embedded deep learning, including neural networks Brings together neural network algorithm and hardware design optimization approaches to deep learning, alongside real-world applications Considers how Edge computing solves privacy, latency and power consumption concerns related to the use of the Cloud Describes how to maximize the performance of deep learning on Edge-computing devices Presents the latest research on neural network compression coding, deep learning algorithms, chip co-design and intelligent monitoring
This book explores and motivates the need for building homogeneous and heterogeneous multi-core systems for machine learning to enable flexibility and energy-efficiency. Coverage focuses on a key aspect of the challenges of (extreme-)edge-computing, i.e., design of energy-efficient and flexible hardware architectures, and hardware-software co-optimization strategies to enable early design space exploration of hardware architectures. The authors investigate possible design solutions for building single-core specialized hardware accelerators for machine learning and motivates the need for building homogeneous and heterogeneous multi-core systems to enable flexibility and energy-efficiency. The advantages of scaling to heterogeneous multi-core systems are shown through the implementation of multiple test chips and architectural optimizations.
In recent years, there has been a remarkable surge in the volume of digital data across various formats and domains. For instance, modern camera systems leverage new technologies and the fusion of information from multiple views to capture high-quality images. As a result of this data explosion, there is a growing interest and demand for analyzing information using data-intensive machine learning algorithms, particularly deep neural networks (DNNs). However, despite the success of deep learning approaches in various domains, their performance on small edge devices with constrained computing power and memory are limited. The primary objective of this thesis is to design efficient intelligent vision systems that effectively overcome the limitations of deep neural networks (DNNs) when deployed on edge devices with limited resources. This work explores a variety of methods aimed at optimizing the utilization of information and context in the design of DNN architectures. By leveraging these techniques, the proposed systems aim to enhance the performance and efficiency of DNNs in resource-constrained environments. Specifically, the thesis proposes context-aware methods to differentiate between low and high quality sensors representations by incorporating the context into the CNN models and reduce the computation and communication costs of edge devices in a distributed camera system. The primary objective is to minimize the computation and communication costs associated with edge devices in a distributed camera system. In addition, the thesis proposes a fault-tolerant mechanism to address the challenges posed by abnormal and noisy data in the system, particularly due to unknown conditions. This mechanism serves as a solution to mitigate the adverse effects of such data, ensuring the reliability and robustness of the proposed system. Furthermore, a resolution-aware multi-view design is outlined to address data transmission and power challenges in embedded devices. Moreover, the thesis introduces a patch-based attention-likelihood technique, designed to enhance the recognition performance of small objects within high-resolution images. This technique effectively reduces the computational burden of handling high-resolution images on edge devices by processing sub-samples of the input patches. By selectively attending to relevant patches, the proposed approach significantly improves the overall efficiency of object recognition while maintaining a high level of accuracy. Finally, the thesis introduces an efficient task-adaptive visual transformer model specifically designed for fine-grained classification tasks on IoT devices. By optimizing the system's performance for IoT devices, it enables efficient and reliable fine-grained classification without compromising computational resources or compromising the accuracy of results. Overall, this thesis offers a comprehensive approach to overcoming the limitations associated with deploying deep neural networks (DNNs) on edge devices within visual intelligent systems.
This book presents recent advances towards the goal of enabling efficient implementation of machine learning models on resource-constrained systems, covering different application domains. The focus is on presenting interesting and new use cases of applying machine learning to innovative application domains, exploring the efficient hardware design of efficient machine learning accelerators, memory optimization techniques, illustrating model compression and neural architecture search techniques for energy-efficient and fast execution on resource-constrained hardware platforms, and understanding hardware-software codesign techniques for achieving even greater energy, reliability, and performance benefits. Discusses efficient implementation of machine learning in embedded, CPS, IoT, and edge computing; Offers comprehensive coverage of hardware design, software design, and hardware/software co-design and co-optimization; Describes real applications to demonstrate how embedded, CPS, IoT, and edge applications benefit from machine learning.
This book presents the latest techniques for machine learning based data analytics on IoT edge devices. A comprehensive literature review on neural network compression and machine learning accelerator is presented from both algorithm level optimization and hardware architecture optimization. Coverage focuses on shallow and deep neural network with real applications on smart buildings. The authors also discuss hardware architecture design with coverage focusing on both CMOS based computing systems and the new emerging Resistive Random-Access Memory (RRAM) based systems. Detailed case studies such as indoor positioning, energy management and intrusion detection are also presented for smart buildings.
This book presents recent advances towards the goal of enabling efficient implementation of machine learning models on resource-constrained systems, covering different application domains. The focus is on presenting interesting and new use cases of applying machine learning to innovative application domains, exploring the efficient hardware design of efficient machine learning accelerators, memory optimization techniques, illustrating model compression and neural architecture search techniques for energy-efficient and fast execution on resource-constrained hardware platforms, and understanding hardware-software codesign techniques for achieving even greater energy, reliability, and performance benefits. Discusses efficient implementation of machine learning in embedded, CPS, IoT, and edge computing; Offers comprehensive coverage of hardware design, software design, and hardware/software co-design and co-optimization; Describes real applications to demonstrate how embedded, CPS, IoT, and edge applications benefit from machine learning.
This book covers algorithmic and hardware implementation techniques to enable embedded deep learning. The authors describe synergetic design approaches on the application-, algorithmic-, computer architecture-, and circuit-level that will help in achieving the goal of reducing the computational cost of deep learning algorithms. The impact of these techniques is displayed in four silicon prototypes for embedded deep learning. Gives a wide overview of a series of effective solutions for energy-efficient neural networks on battery constrained wearable devices; Discusses the optimization of neural networks for embedded deployment on all levels of the design hierarchy – applications, algorithms, hardware architectures, and circuits – supported by real silicon prototypes; Elaborates on how to design efficient Convolutional Neural Network processors, exploiting parallelism and data-reuse, sparse operations, and low-precision computations; Supports the introduced theory and design concepts by four real silicon prototypes. The physical realization’s implementation and achieved performances are discussed elaborately to illustrated and highlight the introduced cross-layer design concepts.