Published: 2003
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In order to improve MOSFET transistor performance, aggressive scaling of devices has continued. As lateral device dimensions continue to scale down, gate oxide thicknesses must also be scaled down. According to the 2001 International Technology Roadmap for Semiconductor (ITRS) for sub-micron technology, an equivalent oxide thickness (EOT) less than 1.0 nm is required for high performance devices. However, at this thickness SiO2 has reached its scaling limit due to the high tunneling current, especially in low power devcies. The use of high K dielectrics may circumvent this impediment since physically thicker dielectrics can be used to reduce gate leakage while maintaining the same level of inversion charge. In this study, we used an alternative, non self-aligned gate process to fabricate both NMOS and PMOS devices with a variety of high K gate dielectric and metal gate electrode materials; finally their electrical properties were characterized. Most high K gate dielectric and gate metal candidates have limited thermal stability. As a result, conventional transistor fabrication process flows cannot be used. Here we developed a non self-aligned gate process, which reverses the order of the junction and the gate stack formation steps and thus allow the use of dielectrics and electrode materials that are not able to sustain high junction activation temperatures. A new mask set, ERC-6, was designed to facilitate the non-self aligned gate process. Wet and dry etching process for alternative high K gate dielectrics (HfO2, ZrO2, La2O3, Y2O3) and metal gate electrodes (Pt, Ru, RuO2, Ta, TaN) were studied. Wet etching of Pt and TaN required periodic re-baking of the photoresist to re-establish adhesion to the substrate. Reactive ion etch (RIE) processes were developed for RuO2, Ru/W, Ta/W gate electrodes. A mixture of oxygen and fluorine plasma was effective in patterning RuO2 electrodes. However, for Ru gate electrodes, e.
