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"The book provides invaluable information to scientists, engineers, and product managers involved with imaging CCDs, as well as those who need a comprehensive introduction to the subject."--Page 4 de la couverture
Solid-State Imaging with Charge-Coupled Devices covers the complete imaging chain: from the CCD's fundamentals to the applications. The book is divided into four main parts: the first deals with the basics of the charge-coupled devices in general. The second explains the imaging concepts in close relation to the classical television application. Part three goes into detail on new developments in the solid-state imaging world (light sensitivity, noise, device architectures), and part four rounds off the discussion with a variety of applications and the imager technology. The book is a reference work intended for all who deal with one or more aspects of solid- state imaging: the educational, scientific and industrial world. Graduates, undergraduates, engineers and technicians interested in the physics of solid-state imagers will find the answers to their imaging questions. Since each chapter concludes with a short section `Worth Memorizing', reading this short summary allows readers to continue their reading without missing the main message from the previous section.
This meeting on "Miniaturization of High Energy Physics Detectors" had two principal aims: on the one hand to offer a Danoramic view, as comprehensive as possible, of this new field whose increasing interest can be understood by means of the justified hope to reach completely unconventional experimental aDparata for high energy physics in a short time: on the other hand to search for sufficient and, if Dossible, more advanced solutions to reduce the present (but more and more the future) gigantic experimental apparatuses to human dimensions. It is the conviction of this Organizing Committee that the first aim has been successfully achieved but for the second one there is still much to do; and so in the near future we foresee a new collective thinking over the progress in this field. Apologising for the delayed publication of these proceedings, due to technical reasons, the Organizing Committee thanks Prof. R. Favilli, Magnifico Rettore of the Pisa University, for his precious contribution to the realisation of the meeting and L. Bulleri, the Mayor of Pisa, for the warm welcome to the participants.
The early era of neural network hardware design (starting at 1985) was mainly technology driven. Designers used almost exclusively analog signal processing concepts for the recall mode. Learning was deemed not to cause a problem because the number of implementable synapses was still so low that the determination of weights and thresholds could be left to conventional computers. Instead, designers tried to directly map neural parallelity into hardware. The architectural concepts were accordingly simple and produced the so called interconnection problem which, in turn, made many engineers believe it could be solved by optical implementation in adequate fashion only. Furthermore, the inherent fault-tolerance and limited computation accuracy of neural networks were claimed to justify that little effort is to be spend on careful design, but most effort be put on technology issues. As a result, it was almost impossible to predict whether an electronic neural network would function in the way it was simulated to do. This limited the use of the first neuro-chips for further experimentation, not to mention that real-world applications called for much more synapses than could be implemented on a single chip at that time. Meanwhile matters have matured. It is recognized that isolated definition of the effort of analog multiplication, for instance, would be just as inappropriate on the part ofthe chip designer as determination of the weights by simulation, without allowing for the computing accuracy that can be achieved, on the part of the user.