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In today's System-on-Chip (SoC) design, both analog and digital circuits play important role. Digital circuits are fully used to build memory and signal processing blocks. With technology scaling, speed of digital circuits has been boosted a lot in deep submicron technologies. Being the interface between real world and digital block, Analog-to-Digital Converter (ADC) is now very critical. Since high speed and high precision is required, ADC has now become a bottleneck in SoC design. Especially when integrated with digital circuits, ADC has to maintain its performance in noisy environment. Therefore, effort is deserved to develop high resolution, low power ADC designs. In this thesis, an 11-bit Pipelined ADC with Op Amp sharing technique is presented. The post-layout simulation shows an SNDR of 59.46dB and SFDR of 69.00dB. Current consumption is around 11mA from 2.5V power supply.
Low-power and small size analog to digital converters (ADCs) are the strategic building blocks in state of the art mobile wireless communication systems. Various techniques have been developed to reduce both power consumption and die area of the ADC. Among these, the opamp-sharing technique shows the most promise. In opamp-sharing, power and die area are saved by sharing one opamp between two successive pipeline stages. However, this technique suffers from the well-known memory effect drawback due to the absence of the reset phase that discharges the opamp's input parasitics. In this dissertation, this drawback is solved by introducing a discharge phase before the opamp is used for the pipeline stages without compromising speed and resolution of the ADC. Further power and area reduction is achieved by using a capacitor-sharing technique. This technique reduces the effective load capacitance of the opamp by reusing the charge on the feedback capacitor for the MDAC operation of the following stage, resulting in faster settling without increasing opamp power. The proposed low input-capacitance variable-gm opamp also helps to reduce the memory effect and improves the settling behavior of the stage output by increasing the bandwidth of the opamp while input parasitics of the opamp are kept small. The prototype designs of a 10-bit 50MSample/s pipelined ADC and a 14-bit 100MSample/s pipelined ADC implemented in 0.181m CMOS technology demonstrate the effectiveness of the proposed techniques. The first ADC achieves 56.2dB SNDR and 72.7dB SFDR for a Nyquist input at full sampling rate while consuming 12 mW from a 1.8-V supply. The FOM, defined as, [power/2[superscript ENOB]. Fs], is 0.46 pJ/step with Fin = 24.5MHz at 50MS/s. The second ADC achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input and consumes 230mW from a 3V supply. The FOM of the second ADC is 0.69 pJ/step with Fin = 46MHz at 100MS/s.
Designing a high-gain, high-bandwidth op-amp for pipelined ADCs in fine-line CMOS technology has become increasingly challenging. In order to address this issue, this thesis presents the shadow-ADC-assisted digital calibration technique. The proposed technique relaxes op-amp performance requirements by removing op-amp-induced charge-transfer errors in the digital domain. A proof-of-concept pipelined ADC has been designed in 28nm FDSOI CMOS technology and is currently being fabricated.
A number of digital applications e.g. professional cameras, voice communication, video digitizers, data imaging and many more require low power, high speed, and high resolution analog to digital converters. But for high speed data communication systems with increased resolution and high sampling rates, different linear and nonlinear errors of ADCs come in picture which is a big challenge for design engineers to remove.A unique digital background calibration technique, a combination of signal dependent dithering with butterfly shuffler is proposed here for multi-bit, SHA-less 16-bit, 125 MS/s Pipelined ADC. The purpose of the research work was to integrate different stages of different sizes to achieve 16-bit error-free output at high sampling rate by using unique background calibration technique for SHA-less circuit. Because the achieved values of SNDR and SFDR are high with low power consumption, so this proposed ADC is suitable for high resolution applications like video communication. Without using sample and hold amplifier we saved power and reduced noise interference. Additional advantage of SHA removal is to use a smaller input sampling capacitor which increases ADC's drivability. A new timing diagram is also proposed here to resolve the sampling clock skew. The ultimate multi-bit front-end proposed here helped to save further power.The proposed comparator is able to avoid the kickback as compared to traditional comparators. For the initial multi-bit stage, a two-stage gain boosted amplifier is used to achieve high gain and to reduce the nonlinear gain errors. Because the non-idealities of Op-amp and capacitor mismatching errors, the ADC transfer function may achieve erroneous values by DNL errors, so the proposed technique is made capable to remove linear gain and offset errors and capacitor mismatching errors. Also the small signal linearity errors removed with the proposed architecture of 16-bit Pipelined ADC. Along with these advantages, high values of SNDR and SFDR has achieved, which is a top most indicator to distinguish the signal out from other noise and spurious frequencies.
In this thesis, I describe a zero-crossing based pipelined ADC. Unlike traditional pipelined ADCs, this work does not use any op-amps in the signal path. The use of zero-crossing based circuits made it possible to achieve a much better figure of merit. The ADC is design to operate at 200MS/s with a resolution of 12 bits. The simulated results suggest that the target performance is achievable with less than 10 mW of power. This design's figure of merit is at least an order of magnitude better than any existing designs that have comparable speed and accuracy performance. The design will be fabricated later to be tested in silicon.
A book is like a window that allows you to look into the world. The window is shaped by the author and that makes that every window presents a unique view of the world. This is certainly true for this book. It is shaped by the topics and the projects throughout my career. Even more so, this book re?ects my own style of working and thinking. That starts already in Chap. 2. When I joined Philips Research in 1979, many of my colleagues used little paper notebooks to keep track of the most used equations and other practical things. This notebook was the beginning for Chap. 2: a collection of topics that form the basis for much of the other chapters. Chapter2 is not intended to explain these topics, but to refresh your knowledge and help you when you need some basics to solve more complex issues. In the chapters discussing the fundamental processes of conversion, you will r- ognize my preoccupation with mathematics. I really enjoy ?nding an equation that properly describes the underlying mechanism. Nevertheless mathematics is not a goalonitsown:theequationshelptounderstandthewaythevariablesareconnected to the result. Real insight comes from understanding the physics and electronics. In the chapters on circuit design I have tried to reduce the circuit diagrams to the s- plest form, but not simpler. . . I do have private opinions on what works and what should not be applied.