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This thesis proposes two new limited global- information-based fault-tolerant routing algorithms for k-ary n-cubes, namely the unsafety vectors algorithm and the probability vectors algorithm. While the first algorithm uses a deterministic approach, which has been widely employed by other existing algorithms, the second algorithm is the first that uses probability-based fault-tolerant routing. These two algorithms have two important advantages over those already existing in the relevant literature. Both algorithms ensure fault- tolerance under relaxed assumptions, regarding the number of faulty nodes and their locations in the network. Furthermore, the new algorithms are more general in that they can easily be adapted to different topologies, including those that belong to the family of k-ary n-cubes.
Both schemes allow routing decisions to be made dynamically at the nodes along the message path, based on output channel contention among the messages at that node. Virtual cut-through routing, which combines features of circuit and packet switching methodologies, is used. In this paper we develope [sic] approximate analytical models for these two implementations of adaptive routing based on birth and death queueing process; extensive simulation experiments are performed to validate the models as well as to evaluate the performance of the adaptive routing schemes with respect to the deterministic routing."
It provides the simplest known support for deadlock-free adaptive routing in k-ary n-cubes of more than two dimensions (with k > 2). Restricting adaptivity reduces the hardware complexity, improving router speed or allowing additional performance-enhancing network features. The structure of planar-adaptive routers is amenable to efficient implementation."
In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.
This book constitutes the refereed proceedings of the 8th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2008, held in Agia Napa, Cyprus, in June 2008. The 31 revised full papers presented together with 1 keynote talk and 1 tutorial were carefully reviewed and selected from 88 submissions. The papers are organized in topical sections on scheduling and load balancing, interconnection networks, parallel algorithms, distributed systems, parallelization tools, grid computing, and software systems.
Foreword -- Foreword to the First Printing -- Preface -- Chapter 1 -- Introduction -- Chapter 2 -- Message Switching Layer -- Chapter 3 -- Deadlock, Livelock, and Starvation -- Chapter 4 -- Routing Algorithms -- Chapter 5 -- CollectiveCommunicationSupport -- Chapter 6 -- Fault-Tolerant Routing -- Chapter 7 -- Network Architectures -- Chapter 8 -- Messaging Layer Software -- Chapter 9 -- Performance Evaluation -- Appendix A -- Formal Definitions for Deadlock Avoidance -- Appendix B -- Acronyms -- References -- Index.
This book contains the refereed proceedings of a DIMACS Workshop on Massively Parallel Computation.