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Statistical timing analysis is an area of growing importance in nanometer te- nologies‚ as the uncertainties associated with process and environmental var- tions increase‚ and this chapter has captured some of the major efforts in this area. This remains a very active field of research‚ and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits‚ a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book‚ the reader is referred to [LNPS00‚ HN01‚ JH01‚ ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs.
This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.
This book introduces state-of-the-art verification techniques for real-time embedded systems, based on the inverse method for parametric timed automata. It reviews popular formalisms for the specification and verification of timed concurrent systems and, in particular, timed automata as well as several extensions such as timed automata equipped with stopwatches, linear hybrid automata and affine hybrid automata. The inverse method is introduced, and its benefits for guaranteeing robustness in real-time systems are shown. Then, it is shown how an iteration of the inverse method can solve the good parameters problem for parametric timed automata by computing a behavioral cartography of the system. Different extensions are proposed particularly for hybrid systems and applications to scheduling problems using timed automata with stopwatches. Various examples, both from the literature and industry, illustrate the techniques throughout the book. Various parametric verifications are performed, in particular of abstractions of a memory circuit sold by the chipset manufacturer ST-Microelectronics, as well as of the prospective flight control system of the next generation of spacecraft designed by ASTRIUM Space Transportation. Contents: 1. Parametric Timed Automata. 2. The Inverse Method for Parametric Timed Automata. 3. The Inverse Method in Practice: Application to Case Studies. 4. Behavioral Cartography of Timed Automata. 5. Parameter Synthesis for Hybrid Automata. 6. Application to the Robustness Analysis of Scheduling Problems. 7. Conclusion and Perspectives. About the Authors Étienne André is Associate Professor in the Laboratoire d’Informatique de Paris Nord, in the University of Paris 13 (Sorbonne Paris Cité) in France. His current research interests focus on the verification of real-time systems. Romain Soulat is currently completing his PhD at the LSV laboratory at ENS-Cachan in France, focusing on the modeling and verification of hybrid temporal systems.
Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field. Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools. From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc.
This book constitutes the refereed proceedings of the 14th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2004, held in Santorini, Greece in September 2004. The 85 revised papers presented together with abstracts of 6 invited presentations were carefully reviewed and selected from 152 papers submitted. The papers are organized in topical sections on buses and communication, circuits and devices, low power issues, architectures, asynchronous circuits, systems design, interconnect and physical design, security and safety, low-power processing, digital design, and modeling and simulation.
Uncertainty in key parameters within a chip and between different chips in the deep sub micron area plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process. Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development. This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits. Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.
This book constitutes the refereed proceedings of the 24th International Colloquium on Automata, Languages and Programming, ICALP '97, held in Bologna, Italy, in July 1997. ICALP '97 celebrated the 25th anniversary of the European Association for Theoretical Computer Science (EATCS), which has sponsored the ICALP meetings since 1972. The volume presents 73 revised full papers selected from a total of 197 submissions. Also included are six invited contributions. ICALP is one of the few flagship conferences in the area. The book addresses all current topics in theoretical computer science.
In 2007 The Design, Automation and Test in Europe (DATE) conference celebrated its tenth anniversary. As a tribute to the chip and system-level design and design technology community, this book presents a compilation of the three most influential papers of each year. This provides an excellent historical overview of the evolution of a domain that contributed substantially to the growth and competitiveness of the circuit electronics and systems industry.
The topic areas presented within this volume focus on design environments and the applications of hardware description and modelling – including simulation, verification by correctness proofs, synthesis and test. The strong relationship between the topics of CHDL'91 and the work around the use and re-standardization of the VHDL language is also explored. The quality of this proceedings, and its significance to the academic and professional worlds is assured by the excellent technical programme here compiled.