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Total on-chip interconnect length has been increasing exponentially with technology scaling. Consequently, interconnect-driven design is an emerging trend in state-of-the- art integrated circuits. Cu-based interconnect technology is expected to meet some of the challenges of technology scaling. However, Cu interconnects still pose a reliability concern due to electromigration-induced failure over time. The major contribution of this thesis is a new reliability CAD tool, SysRel, for thermal-aware reliability analysis with either Al or Cu metallization technology in conventional and three-dimensional integrated circuits. An interconnect tree is the fundamental reliability unit for circuit-level reliability assessments for metallization schemes with fully-blocking boundaries at the vias. When vias do not block electromigration as indicated in some Cu experimental studies, multiple trees linked by a non-blocking via are merged to create a single fundamental reliability unit. SysRel utilizes a tree-based hierarchical analysis that sufficiently captures the differences between electromigration behavior in Al and Cu metallizations. The hierarchical flow first identifies electromigration-critical nets or "mortal" trees, applies a default model to estimate the lifetimes of individual trees, and then produces a set of full-chip reliability metrics based on stochastic analysis using the desired lifetime of the circuit. We have exercised SysRel to compare layout-specific reliability with Cu and Al metallizations in various circuits and circuit elements. Significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability. The required improvement will increase as low-k dielectric materials are introduced and liner thicknesses are reduced in future.
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Cutting-Edge CMOS VLSI Design for Manufacturability Techniques This detailed guide offers proven methods for optimizing circuit designs to increase the yield, reliability, and manufacturability of products and mitigate defects and failure. Covering the latest devices, technologies, and processes, Nanoscale CMOS VLSI Circuits: Design for Manufacturability focuses on delivering higher performance and lower power consumption. Costs, constraints, and computational efficiencies are also discussed in the practical resource. Nanoscale CMOS VLSI Circuits covers: Current trends in CMOS VLSI design Semiconductor manufacturing technologies Photolithography Process and device variability: analyses and modeling Manufacturing-Aware Physical Design Closure Metrology, manufacturing defects, and defect extraction Defect impact modeling and yield improvement techniques Physical design and reliability DFM tools and methodologies